View FWIXP420BC_2244097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document number: 252479, revision: 005 march 2005 intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet product features for a complete list of product features, see ?product features? on page 11 . typical applications the following features do not require enabling software: intel xscale ? core ? up to 533 mhz pci interface usb v1.1 device controller sdram interface high-speed uart console uart internal bus performance monitoring unit 16 gpios four internal timers packaging ? 492-pin pbga commercial/exte nded temperature the following features do require enabling software: encryption/authentication (aes,des,3des,sha-1,md5) two high-speed, serial interfaces three network processor engines up to two mii interfaces one utopia-2 interface multi-channel hdlc note: refer to the intel ? ixp400 software programmer?s guide for information on which features are currently enabled. high-performance dsl modem high-performance cable modem residential gateway sme router network printers control plane integrated access device (iad) set-top box access points (802.11a/b/g) industrial controllers
march 2005 datasheet 2 document number: 252479, revision: 005 legal lines and disclaimers information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furn ishing of documents and other materials and info rmation does not provide any license, express or implied, by estoppel or otherwise, to any such patents, tradem arks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. intel processor numbers are not a measure of performance. proce ssor numbers differentiate features within each processor family , not across different processor families. see http://www.intel.com/products/processor_number for details. the intel ? ixp42x product line of network processors and ixc1100 control plane processor may contain design defects or errors known as er rata which may cause the product to deviate from published specifications. current charac terized errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . bunnypeople, celeron, chips, dialogic, etherexpress, etox, flashfile, i386, i486, i960, icomp, instantip, intel, intel centrino , intel centrino logo, intel logo, intel386, intel486, intel740, inteldx2, inteldx4, intelsx2, intel inside, intel inside logo, intel netburst, intel netmerge, intel netstructure, intel singledriver, intel speedstep, intel strataflash, intel x eon, intel xscale, iplink, itanium, mcs, mmx, mmx logo, optimize r logo, overdrive, paragon, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, sound mark, the computer inside, the journey inside, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 3 contents 1.0 introduction ............................................................................................................................... ..... 9 1.1 about this document ......................................................................................................... ...9 1.2 product features ............................................................................................................ .... 11 1.2.1 product line features ........................................................................................... 11 1.2.2 processor features ............................................................................................... 14 2.0 functional overview ................................................................................................................... 15 2.1 functional units ............................................................................................................ ...... 20 2.1.1 network processor engines (npes) ...................................................................... 20 2.1.2 internal bus............................................................................................................ 21 2.1.2.1 north ahb ..............................................................................................21 2.1.2.2 south ahb ............................................................................................. 22 2.1.2.3 apb bus................................................................................................. 22 2.1.3 mii interfaces ......................................................................................................... 22 2.1.4 utopia 2 .............................................................................................................. 23 2.1.5 usb interface ........................................................................................................ 23 2.1.6 pci controller ........................................................................................................ 23 2.1.7 sdram controller ................................................................................................. 23 2.1.8 expansion bus ....................................................................................................... 24 2.1.9 high-speed, seri al interfaces ................................................................................ 24 2.1.10 high-speed and console uarts .......................................................................... 25 2.1.11 gpio ..................................................................................................................... .25 2.1.12 internal bus performanc e monitoring unit (ibpmu) .............................................. 25 2.1.13 interrupt contro ller ................................................................................................. 25 2.1.14 timers ................................................................................................................... .26 2.1.15 ahb queue manager ............................................................................................ 26 2.2 intel xscale ? core .............................................................................................................. 26 2.2.1 super pipeline ....................................................................................................... 27 2.2.2 branch target buffer (btb) ................................................................................... 28 2.2.3 instruction memory management unit (immu) ...................................................... 29 2.2.4 data memory management unit (dmmu) ............................................................. 29 2.2.5 instruction cache (i-cache) ................................................................................... 29 2.2.6 data cache (d-cache) .......................................................................................... 30 2.2.7 mini-data cache .................................................................................................... 30 2.2.8 fill buffer (fb) and pend buffer (pb)..................................................................... 31 2.2.9 write buffer (wb)................................................................................................... 31 2.2.10 multiply-accumulate coprocessor (cp0) ............................................................... 31 2.2.11 performance monitoring unit (pmu)...................................................................... 32 2.2.12 debug unit ............................................................................................................. 32 3.0 functional signal descriptions .................................................................................................. 33 4.0 package and pinout information ................................................................................................ 50 4.1 package description ......................................................................................................... ..50 4.2 signal-pin descriptions..................................................................................................... .. 53 4.3 package thermal specifications ........................................................................................ 81 4.3.1 commercial temperature ...................................................................................... 81
intel ? ixp42x product line of network processors and ixc1100 control plane pro- cessor march 2005 datasheet 4 document number: 252479, revision: 005 4.3.2 extended temperature .......................................................................................... 81 5.0 electrical specifications ............................................................................................................. 82 5.1 absolute maximum ratings ................................................................................................ 82 5.2 v ccpll1 , v ccpll2 , v ccoscp , v ccosc pin requirements .................................................. 82 5.2.1 v ccpll1 requirement ............................................................................................ 82 5.2.2 v ccpll2 requirement ............................................................................................ 83 5.2.3 v ccoscp requirement .......................................................................................... 83 5.2.4 v ccosc requirement ............................................................................................ 84 5.3 rcomp pin requirements................................................................................................. 85 5.4 dc specifications ........................................................................................................... .... 85 5.4.1 operating conditions ............................................................................................. 85 5.4.2 pci dc parameters ............................................................................................... 86 5.4.3 usb dc parameters.............................................................................................. 86 5.4.4 utopia-2 dc parameters .................................................................................... 87 5.4.5 mii dc parameters ................................................................................................ 87 5.4.6 mdio dc parameters............................................................................................ 88 5.4.7 sdram bus dc parameters................................................................................. 88 5.4.8 expansion bus dc parame ters ............................................................................. 88 5.4.9 high-speed, serial interface 0 dc parameters..................................................... 89 5.4.10 high-speed, seri al interface 1 dc parameters..................................................... 89 5.4.11 high-speed and console uart dc parameters .................................................. 90 5.4.12 gpio dc parameters ............................................................................................ 90 5.4.13 jtag dc parameters............................................................................................ 90 5.4.14 reset dc parameters............................................................................................ 91 5.5 ac specifications........................................................................................................... ..... 91 5.5.1 clock signal timings ............................................................................................. 91 5.5.1.1 processor clock timings ....................................................................... 91 5.5.1.2 pci clock timings ................................................................................. 94 5.5.1.3 mii clock timings .................................................................................. 94 5.5.1.4 utopia-2 clock timings....................................................................... 94 5.5.1.5 expansion bus clock timings ............................................................... 94 5.5.2 bus signal timings ................................................................................................ 95 5.5.2.1 pci ......................................................................................................... 95 5.5.2.2 usb interface......................................................................................... 96 5.5.2.3 utopia-2 .............................................................................................. 97 5.5.2.4 mii .......................................................................................................... 98 5.5.2.5 mdio...................................................................................................... 99 5.5.2.6 sdram bus......................................................................................... 100 5.5.2.7 expansion bus ..................................................................................... 101 5.5.2.8 high-speed, serial interfaces .............................................................. 125 5.5.2.9 jtag.................................................................................................... 127 5.5.3 reset timings...................................................................................................... 128 5.6 power sequence .............................................................................................................. 129 5.7 i cc and total average power ........................................................................................... 131 6.0 ordering information ................................................................................................................. 133
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 5 figures 1 intel ? ixp425 network processor bl ock diagram ...................................................................... 15 2 intel ? ixp423 network processor bl ock diagram ...................................................................... 16 3 intel ? ixp422 network processor bl ock diagram ...................................................................... 17 4 intel ? ixp421 network processor bl ock diagram ...................................................................... 18 5 intel ? ixp420 network processor bl ock diagram ...................................................................... 19 6 intel xscale ? core block diagram ............................................................................................. 27 7 492-pin lead pbga package ............................. ....................................................................... 5 0 8 package markings .............................................................................................................. ........ 51 9v ccpll1 power filtering diagram ..... .......................................................................................... 83 10 v ccpll2 power filtering diagram ..... .......................................................................................... 83 11 v ccoscp power filtering diagram ............................................................................................. 84 12 v ccosc power filtering diagram ............................................................................................... 84 13 rcomp pin external resistor requirements ..... ....................................................................... 85 14 typical connection to a crystal .............................................................................................. .... 93 15 typical connection to an oscillator .......................................................................................... .. 93 16 pci output timing ............................................................................................................ .......... 95 17 pci input timing ............................................................................................................. ............ 95 18 utopia-2 input timings....................................................................................................... ...... 97 19 utopia-2 output timings...................................................................................................... .... 97 20 mii output timings ........................................................................................................... .......... 98 21 mii input timings ............................................................................................................ ............ 98 22 mdio output timings .......................................................................................................... ....... 99 23 mdio input timings........................................................................................................... ......... 99 24 sdram input timings .......................................................................................................... ....100 25 sdram output timings ......................................................................................................... ..100 26 signal timing with respect to clock rising edge ...................................................................101 27 intel ? multiplexed read mode ..................................................................................................102 28 intel ? multiplexed write mode ..................................................................................................103 29 intel ? simplex read mode........................................................................................................105 30 intel ? simplex write mode........................................................................................................105 31 motorola* multiplexed read mode.................... ........................................................................10 7 32 motorola* multiplexed write mode.................... ........................................................................1 08 33 motorola* simplex read mode .. ...............................................................................................1 10 34 motorola* simplex write mode ................................................................................................. 111 35 hpi-8 mode read accesses..................................................................................................... 113 36 hpi-8 mode write accesses.................................................................................................... .114 37 hpi-16 multiplexed write mode ................................................................................................ 118 38 hpi-16 multiplex read mode................................................................................................... .120 39 hpi-16 simplex read mode ..................................................................................................... 122 40 hpi-16 simplex write mode .................................................................................................... .124 41 high-speed, serial timings ................................................................................................... ...125 42 boundary-scan general timings......................... .....................................................................12 7 43 boundary-scan reset timings .................................................................................................1 27 44 reset timings................................................................................................................ ...........128 45 power-up sequence timing...... ............................................................................................... 130
intel ? ixp42x product line of network processors and ixc1100 control plane pro- cessor march 2005 datasheet 6 document number: 252479, revision: 005 tables 1 related documents ............................................................................................................. ......... 9 2 terminology and acronyms ...................................................................................................... .... 9 3 processor features ............................................................................................................ ........ 14 4 processor functions........................................................................................................... ........ 20 5 signal type definitions................................. ...................................................................... ........ 33 6 sdram interface............................................................................................................... ......... 34 7 pci controller ................................................................................................................ ............. 36 8 high-speed, serial in terface 0 ................................................................................................ ... 38 9 high-speed, serial in terface 1 ................................................................................................ ... 39 10 mii interfaces............................................................................................................... ............... 40 11 utopia-2 interface ........................................................................................................... ......... 42 12 expansion bus interface...................................................................................................... ....... 44 13 uart interfaces .............................................................................................................. ........... 45 14 usb interface ................................................................................................................ ............. 46 15 oscillator interface......................................................................................................... ............. 46 16 gpio interface............................................................................................................... ............. 46 17 jtag interface ............................................................................................................... ............ 47 18 system interface............................................................................................................. ............ 48 19 power interface .............................................................................................................. ............ 48 20 part numbers ................................................................................................................. ............ 51 21 ball map assignment for the intel ? ixp425 network pr ocessor................................................. 53 22 ball map assignment for the intel ? ixp422 network pr ocessor................................................. 60 23 ball map assignment for the intel ? ixp421 network pr ocessor................................................. 67 24 ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor ............................................................................. 74 25 operating conditions......................................................................................................... ......... 85 26 pci dc parameters ............................................................................................................ ........ 86 27 usb v1.1 dc parameters....................................................................................................... .... 86 28 utopia-2 dc parameters ....................................................................................................... .. 87 29 mii dc parameters............................................................................................................ ......... 87 30 mdio dc parameters ........................................................................................................... ..... 88 31 sdram bus dc parameters............................... ....................................................................... 88 32 expansion bus dc parameters.................................................................................................. 88 33 high-speed, serial in terface 0 dc parameters.......................................................................... 89 34 high-speed, serial in terface 1 dc parameters.......................................................................... 89 35 uart dc parameters ........................................................................................................... ..... 90 36 gpio dc parameters ........................................................................................................... ...... 90 37 jtag dc parameters................ ........................................................................................... ...... 90 38 pwron_reset_n dc parameters ........................ ................................................................. 91 39 device clock timings (oscillator reference) ...... ....................................................................... 91 40 device clock timings (crystal reference) ....... .......................................................................... 92 41 pci clock timings ............................................................................................................ .......... 94 42 mii clock timings ............................................................................................................ ........... 94 43 utopia-2 clock timings ....................................................................................................... .... 94 44 expansion bus clock timings .................................................................................................. .. 94 45 pci bus signal timings ....................................................................................................... ....... 96 46 utopia-2 input timings values ...................... .......................................................................... 97 47 utopia-2 output timings values....................... ....................................................................... 9 7
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 7 48 mii output timings values .................................................................................................... ..... 98 49 mii input timings values ..................................................................................................... ....... 98 50 mdio timings values.......................................................................................................... ....... 99 51 sdram input timings values ..................................................................................................1 00 52 sdram output timings values ...............................................................................................100 53 signal timing with respect to clock rising edge ...................................................................101 54 intel ? multiplexed mode values................................................................................................104 55 intel simplex mode values .................................................................................................... ...106 56 motorola* multiplexed mode values .........................................................................................109 57 motorola* simplex mode values...............................................................................................1 12 58 hpi timing symbol description ................................................................................................ 115 59 hpi-8 mode write access values..................... ........................................................................11 5 60 hpi-16 multiplexed write accesses values..............................................................................117 61 hpi-16 multiplexed read accesses values .............................................................................119 62 hpi-16 simplex read accesses values...................................................................................121 63 hpi-16 simplex write accesses values ...................................................................................123 64 high-speed, serial timing values............................................................................................1 26 65 boundary-scan interface timings values ........... .....................................................................127 66 reset timings table parameters .............................................................................................12 9 67 i cc and total average power ? co mmercial temperature range...........................................131 68 i cc and total average power ? ex tended temperature range...............................................132
intel ? ixp42x product line of network processors and ixc1100 control plane pro- cessor march 2005 datasheet 8 document number: 252479, revision: 005 revision history date revision description march 2005 005 1. rearranged product features lists in section 1.2, ?product features? 2. added two new columns to table 3 to indicate software enable/disable, and ixp423 network processor features 3. replaced network processor block diagrams: figure 1 , figure 2 , figure 3 , figure 4 , and figure 5 4. added new row for the ixp423 network processor to table 4, ?processor functions? 5. corrected the pci_idsel definition in table 7, ?pci controller? 6. added pull-up resistor requirement for the eth_mdio pin in table 10, ?mii interfaces? 7. added footnote to table 18, ?system interface??? regarding system level reset 8. added part number for ixp423 on table 20, ?part numbers? 9. added note 4 to table 26, ?pci dc parameters? 10. changed vih ?minimum? parameter to 2.0 in table 27, ?usb v1.1 dc parameters? (see the intel ? ixp4xx product line of network proc essors specification update (306428)); added note 2 11. added new paragraph to section 5.5.1.1, ?processor clock timings? regarding crystal os cillators application 12. added footnote regarding pll operation at the lowest slew rate to table 39, ?device clock timings (oscillator reference)? and table 40, ?devic e clock timings (crystal reference)? 13. added footnote to table 49, ?mii input timings values? and table 50, ?mdio timings values? 14. inserted new figure 26, ?signal timing with respect to clock rising edge? 15. replaced expansion bus figures: figure 26 ? figure 40 16. updated table 53, ?signal timing with respect to clock rising edge? 17. updated trdsetup and trdhold values in table 54 , table 55 , table 56 and table 57 18. added footnotes to table 61, ?hpi-16 multiplexed read accesses values? 19. replaced table 67, ?icc and total average power ? commercial temperature range? , and inserted new table 68, ?icc and total average power ? extended temperature range? june 2004 004 updated intel ? product branding. change bars are retained from the previous release of this document (-003). april 2004 003 incorporated specification changes, specification clarifications and document changes from the intel ? ixp42x product line of network processors and ixc1100 control plane processor specification update (252702-003). may 2003 002 incorporated specification changes, specification clarifications and document changes from the intel ? ixp42x product line of network processors specification update (252702-001). incorporated information for the intel ? ixc1100 control plane processor. february 2003 001 initial release of this document. document reissued, without ?confidential? marking.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 9 1.0 introduction 1.1 about this document this datasheet contains a func tional overview of the intel ? ixp42x product line of network processors and ixc1100 control plane processor, as well as mechanical data (package signal locations and simulated thermal ch aracteristics), targeted electri cal specifications, and some bus functional wave forms for the device. detailed f unctional descriptions ? other than parametric performance ? are published in the intel ? ixp42x product line of network processors and ixc1100 control plane pro cessor developer?s manual . other related documents are shown in table 1 . table 1. related documents document title document # intel ? ixp4xx product line of network processors specification update 306428 intel ? ixp42x product line of network processo rs and ixc1100 control plane processor developer?s manual 252480 intel ? ixp400 software programmer?s guide 252539 intel ? ixp400 software specification update 273795 intel xscale ? core developer?s manual 273473 intel ? ixp42x product line of network processo rs and ixc1100 control plane processor hardware design guidelines 252817 intel xscale ? microarchitecture technical summary ? pci local bus specification , rev. 2.2 ? universal serial bus specification , revision 1.1 ? pc133 sdram specification ? table 2. terminology and acronyms acronym/ terminology description aal atm adaptation layers aes advanced encryption standard ahb advanced high-performance bus apb advanced peripheral bus api application program interface assert the logically active value of a signal or bit. atm asynchronous transmission mode aqm ahb queue manager btb branch target buffer crc cyclical redundancy check deassert the logically inactive value of a signal or bit.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 10 document number: 252479, revision: 005 ddr double data rate des data-encryption standard dma direct memory access dsp digital signal processor e1 euro 1 trunk line fifo first in first out gci general circuit interface gpio general-purpose input/output hdlc high-level data link control hpi (texas instruments*) host port interfaces hss high-speed serial (port) lsb least-significant bit lsb least-significant byte mac media access controller mdio management data input/output mii media-independent interface mmu memory management unit msb most-significant bit msb most-significant byte npe network processor engine pci peripheral component interconnect phy physical layer (layer 1) interface reserved a field that may be used by an implementation. software should not modify reserved fields or depend on any values in reserved fields. rx receive (hss is receiving from off-chip) sram static random access memory sdram synchronous dynamic random access memory t1 type 1 trunk line tx transmit (hss is transmitting off-chip) uart universal asynchronous receiver-transmitter usb universal serial bus utopia universal test and operations phy interface for atm wan wide area network table 2. terminology a nd acronyms (continued) acronym/ terminology description
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 11 1.2 product features 1.2.1 product line features table 3 on page 14 describes which features apply to the intel ? ixp42x product line of network processors and ixc1100 control plane processor. ? intel xscale ? core (compliant with arm * architecture) ? high-performance processor based on intel xscale ? microarchitecture ? seven/eight-stage intel ? super-pipelined risc technology ? management unit ? 32-entry, data memory management unit ? 32-entry, instruction memory management unit ? 32-kbyte, 32-way, set as sociative instruction cache ? 32-kbyte, 32-way, set associative data cache ? 2-kbyte, two-way, set as sociative mini-data cache ? 128-entry, branch target buffer ? eight-entry write buffer ? four-entry fill and pend buffers ? clock speeds: ? 266 mhz ? 400 mhz ? 533 mhz ?arm * version v5te compliant ?intel ? media processing technology multiply-accumulate coprocessor ? debug unit accessible through jtag port ? pci interface ? 32-bit interface ? selectable clock ? 33 mhz clock output derived from either gpio14 or gpio15 ? 33 and 66 mhz clock input ? pci local bus specification , rev. 2.2 compatible ? pci arbiter supporting up to four ex ternal pci devices (four req/gnt pairs) ? host/option capable ? master/target capable ? two dma channels ? usb v 1.1 device controller ? full-speed capable ? embedded transceiver
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 12 document number: 252479, revision: 005 ? 16 endpoints ? sdram interface ? 32-bit data ? 13-bit address ?133mhz ? up to eight open pages simultaneously maintained ? programmable auto-refresh ? programmable cas/data delay ? support for 8 mb, minimum, up to 256 mb maximum ? expansion interface ? 24-bit address ? 16-bit data ? eight programmable chip selects ? supports intel/motorola* microprocessors ? multiplexed-style bus cycles ? simplex-style bus cycles ? dsp support for: ? texas instruments* dsps supporting hpi-8 bus cycles ? texas instruments dsps supporting hpi-16 bus cycles ? high-speed/console uarts ? 1,200 baud to 921 kbaud ? 16550 compliant ? 64-byte tx and rx fifos ? cts and rts modem control signals ? internal bus performance monitoring unit ? seven 27-bit event counters ? monitoring of internal bus occurrences and duration events ? 16 gpios ? four internal timers ? packaging ?492-pin pbga ? commercial temperature (0 to +70 c) ? extended temperature (-40 to +85 c) the following features can be enabled by software, consult the intel ? ixp400 software programmer?s guide to determine if a feature can be enabled for a particular product. ? three network processor engines (npes)
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 13 used to offload typical layer-2 networking functions such as: ? ethernet filtering ?atm saring ? hdlc ? encryption/authentication ?des ?des3 ? aes 128-bit and 256-bit ? two mii interfaces ? 802.3 mii interfaces ? single mdio interface to control both mii interfaces ? utopia-2 interface ? eight-bit interface ? up to 33 mhz clock speed ? five transmit and five receive address lines ? two high-speed, serial interfaces ? six-wire ? supports speeds up to 8.192 mhz ? supports connection to t1/e1 framers ? supports connection to codec/slics ? eight hdlc channels
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 14 document number: 252479, revision: 005 1.2.2 processor features table 3. processor features feature requires enabling software (note 1) intel ? ixp425 network processor b0 step intel ? ixp423 network processor intel ? ixp422 network processor intel ? ixp421 network processor intel ? ixp420 network processor intel ? ixc1100 control plane processor processor speed (mhz) 266/400/533 266 266 266 266/400/533 266/400/533 utopia 2 yes x x x gpio xxxxxx uart 0/1 xxxxxx hss 0 yes x x x hss 1 yes x x x mii 0yesxxxxxx mii 1 yes x x x x x usb xxxxxx pci xxxxxx expansion bus 16-bit, 66 mhz 16-bit, 66 mhz 16-bit, 66 mhz 16-bit, 66 mhz 16-bit, 66 mhz 16-bit, 66 mhz sdram 32-bit, 133 mhz 32-bit, 133 mhz 32-bit, 133 mhz 32-bit, 133 mhz 32-bit, 133 mhz 32-bit, 133 mhz aes / des / des3 yes x x multi- channel hdlc yes 8 8 8 sha-1 / md-5 yes x x commercial temperature xxxxxx extended temperature x x (note 2 )x notes: 1. the features marked ?yes? require enabling software. please refer to the intel ? ixp400 software programmer?s guide to determine if the feature is enabled. 2. only the 266 mhz version of the intel ? ixp420 network processor supports extended temperature.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 15 2.0 functional overview the intel ? ixp42x product line of network processo rs and ixc1100 control plane processor are compliant with the arm * version 5te instruction-set architecture (isa). the intel ? ixp42x product line and ixc1100 control plane proce ssors are designed with intel 0.18- production semiconductor process technology. this process t echnology ? along with the compactness of the intel xscale core, the ability to simultaneously process up to thr ee integrated network processing engines (npes), and numerous dedicated-function peripheral interfaces ? enables the ixp42x product line and ixc1100 control plane processors to operate over a wi de range of low-cost networking applications, with industry-leading performance. as indicated in figure 1 through figure 5 , the intel ? ixp42x product line and ixc1100 control plane processors combine many feat ures with the intel xscale core to create a highly integrated processor applicable to lan/wan-based networking applications in addition to other embedded networking applications. this section briefly describes the main features of the product. for detailed functional descriptions, see the intel ? ixp42x product line of network proces sors and ixc1100 control plane processor developer?s manual . figure 1. intel ? ixp425 network processor block diagram

!
" #$% '(
)* + ) )* ", $-."/0 ).1)0 ) )* + ) )* " 2+. + ) ! , #" 3 4 3' $5% '0 $0 $' !" # $ % # %"! #
""
"" +*.
* $ ( +* $ #
& # ' ( )*(+
* $ 6

" ( 7 " " 7 - /8 " 9 : #,,
# - . / # - "( / # -
. / )3
$. ( #
& # ' 0( )*(+
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 16 document number: 252479, revision: 005 figure 2. intel ? ixp423 network processor block diagram

!
" #$% '(
)* + ) )* " )* + ) )* " ,+- + ) ! . #" / 0 /' $1% '2 $2 $' !" # $ % & # # %"! &
""
""# +*-
* $ ( +* $ #&&&
' & ( ) *+),
* $ 3

" ( 4 " " 4 5 67 " 8 9
& - . / & - ") / -
. / )/
$- ( #&&&
' & ( 0) *+),
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 17 figure 3. intel ? ixp422 network processor block diagram

!
" #$% '(
)* + ) )* " !" #$ !" ## ## +*,
* $ ( +* $ !!!"
% !" & '
()'*
* $ -

" ( . " " . / 01 " 2 3 )4
$, ( 2 3 "
!" + , - !" + #' - " + , - !!!"
% !" & .'
()'* )* + ) )* " $/,"05 )5 6)5 )
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 18 document number: 252479, revision: 005 figure 4. intel ? ixp421 network processor block diagram

!
" #$% '(
)* + ) )* " ,+- + ) ! #" . / .' $0% '1 $ !" #$ !" ## +*-
* $ ( +* $ !!!"
% !" & '
()'*
* $ 2

" ( 3 " " 3 4 56 " 7 8 ).
$- ( 7 8 "
!" + , - !" + #' - " + , - .$# "

!!!"
% !" & /'
()'*
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 19 figure 5. intel ? ixp420 network processor block diagram

!
" #$% '(
)* + ) )* " )* + ) )* " !" #$ !" ## ## +*,
* $ ( +* $ !!!"
% !" & '
()'*
* $ -

" ( . " " . / 01 " 2 3 )4
$, ( 2 3 "++!!
!" , - . !" , #' . " , - . !!!"
% !" & /'
()'*
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 20 document number: 252479, revision: 005 2.1 functional units the following sections briefly describe the functio nal units and their interaction in the system. for more detailed information, refer to the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual . unless otherwise specified, the functional descrip tions apply to all processors in the ixp42x product line and ixc1100 control plane processors. refer to table 3 on page 14 and figure 1 on page 15 through figure 5 for specific informati on on supported interfaces 2.1.1 network processor engines (npes) the network processor engines (n pes) are dedicated-function pro cessors containing hardware coprocessors integrated into the ixp42x product line and ixc1100 control plane processors. the npes are used to off-load processing func tions required by th e intel xscale core. these npes are high-performance, hardware-mu lti-threaded processors with additional local- hardware-assist functionality used to off-load hi ghly processor-intensive functions such as mii (mac), crc checking/generation, aal 2, aes, des, sha-1, and md5. all instruction code for the npes are stored locally with a dedicated instruction memory bus and dedicated data memory bus. these npes support processing of the dedicated peripherals that can include: ? a universal test and operation phy interface for atm (utopia) 2 interface ? two high-speed serial (hss) interfaces ? two media-independent interfaces (mii) table 4 specifies which devices, in the ixp42x product line and ixc1100 control plane processors, have which of these capabilities. the npe core is a hardware-multi-threaded proce ssor engine that is used to accelerate functions that are difficult to achieve high performance in a standard risc pr ocessor. each npe core is a 133 mhz processor core that has self-contained instru ction memory and self-contained data memory that operate in parallel. table 4. processor functions device utopia hss mii 0 mii 1 aes / des / des3 multi-channel hdlc sha-1 / md-5 intel ? ixp425 network processor , b-step xxxx x 8 x intel ? ixp423 network processor xxxx 8 intel ? ixp422 network processor xx x x intel ? ixp421 network processor xxx 8 intel ? ixp420 network processor xx intel ? ixc1100 control plane processor xx
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 21 in addition to having separate instruction/data memory and local-code store, the npe core supports hardware multi-threading with support for multiple contexts. the support of hardware multi- threading creates an efficient processor engine with minimal processor stalls due to the ability of the processor core to switch contexts in a singl e clock cycle, based on a prioritized/preemptive basis. the prioritized/preemptive nature of the context switching al lows time-critical applications to be implemented in a low-latency fashion ? wh ich is required when processing multi-media applications. the npe core also connects several hardware-bas ed coprocessors that are used to implement functions that are difficult for a processo r to implement. these functions include: these coprocessors are implemented in hardwa re, enabling the copr ocessors and the npe processor core to operate in parallel. the combined forces of the hardware multi-thr eading, local-code store, independent instruction memory, independent data memory, and parallel pr ocessing allows the in tel xscale core to be utilized for applicatio n purposes. the multi-pro cessing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the intel xscale core. 2.1.2 internal bus the internal bus architecture of the ixp42x product line and ixc1100 control plane processors is designed to allow parallel processing to occur and to isolate bus utilization, based on particular traffic patterns. the bus is segmented into th ree major buses: the north ahb, south ahb, and apb. 2.1.2.1 north ahb the north ahb is a 133.32 mhz, 32-bit bus that can be mastered by the npes. the targets of the north ahb can be the sdram or the ahb/ahb br idge. the ahb/ahb bridge allows the npes to access the peripherals and inte rnal targets on the south ahb. data transfers by the npes on the north ahb to th e south ahb are targeted predominately to the queue manager. transfers to the ahb/ahb bridge may be ?posted,? when writing, or ?split,? when reading. when a transaction is ?posted,? a master on the north ahb requests a write to a peripheral on the south ahb. if the ahb/ah b bridge has a free fifo location, th e write request will be transferred from the master on the north ahb to the ahb/ ahb bridge. the ahb/ahb bridge will complete the write on the south ahb, when it can obtain access to the peripheral on the south ahb. the north ahb is released to complete another transaction. when a transaction is ?split,? a master on the no rth ahb requests a read of a peripheral on the south ahb. if the ahb/ahb bridge has a free fifo location, the read request will be transferred from the master on the north ahb to the ahb/ ahb bridge. the ahb/ahb bridge will complete the read on the south ahb, when it can obtain access to the peripheral on the south ahb. ? serialization/de -serialization ? crc checking/generation ? des/3des/aes ? sha-1 ? md5 ? hdlc bit stuffing/de-stuffing
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 22 document number: 252479, revision: 005 once the ahb/ahb bridge has obtained the read information from the peripheral on the south ahb, the ahb/ahb bridge notifies the arbiter, on the north ahb, that the ahb/ahb bridge has the data for the master that requested the ?split ? transfer. the master on the north ahb ? that requested the split transfer ? will arbitrate for the nort h ahb and transfer the read data from the ahb/ahb bridge. the north ahb is released to complete another transaction while the north ahb master ? that requested the ?split? tr ansfer ? waits for the data to arrive. these ?posting? and ?splitting? transfers allow control of the north ahb to be given to another master on the north ahb ? enabling the north ahb to achieve maximum efficiency. transfers to the ahb/ahb bridge are considered to be small and infrequent, relative to the traffic passed between the npes on the north ahb and the sdram. 2.1.2.2 south ahb the south ahb is a 133.32 mhz, 32-bit bus that can be mastered by the intel xscale ? core, pci controller, and the ahb/ahb bridge. the targets of the south ahb bus can be the sdram, pci interface, queue manager, expans ion bus, or the apb/ahb bridge. accessing across the apb/ahb bridge allows inte rfacing to peripherals attached to the apb. 2.1.2.3 apb bus the apb bus is a 66.66 mhz (which is 2 * osc_in input pin.), 32-bit bus that can be mastered by the ahb/apb bridge only. the targets of the apb bus can be: the apb interface is also used as an alternate-path interface to the npes and is used for npe code download and configuration. 2.1.3 mii interfaces two industry-standard, me dia-independent interface (mii) interfaces are inte grated into most of the ixp42x product lin e and ixc1100 control plane proce ssors with separate media-access controllers and independent network processing engines. (see table 4 on page 20 .) the independent npes and macs allow parallel pr ocessing of data traffic on the mii interfaces and off-loading of processing required by the intel xscale ? core. the ixp42x product line and ixc1100 control plane processors are comp liant with the ieee, 802.3 specification. in addition to two mii interfaces, the ixp42x product line and ixc1100 control plane processors include a single management data interface that is used to confi gure and control p hy devices that are connected to the mii interface. ? high-speed uart interface ? console uart interface ? usb v1.1 interface ? all npes ? internal bus performance monitoring unit (ibpmu) ? interrupt controller ? gpio ? timers
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 23 2.1.4 utopia 2 the integrated, utopia-2 interface works with a network processing engine, for several of the ixp42x product line and ixc1100 control plane processors. (see table 4 on page 20 .) the utopia-2 interface supports a single- or a multiple-physical-interf ace configuration with cell-level or octet-level handshaking. the netw ork processing engine handles segmentation and reassembly of atm cells, crc checking/generation, and transfer of data to/from memory. this allows parallel processing of data traffic on the utopia-2 interface, off-loading processor overhead required by the intel xscale ? core. the ixp42x product line and ixc1100 control pl ane processors are compliant with the atm forum , utopia level-2 specification , revision 1.0. 2.1.5 usb interface the integrated usb 1.1 interface is a device-only controller. the interface supports full-speed operation and 16 endpoints and includes an integrated transceiver. there are: ? six isochronous endpoints (three input and three output) ? one control endpoints ? three interrupt endpoints ? six bulk endpoints (three input and three output) 2.1.6 pci controller the ixp42x product line and ixc1100 control plane processors? pci controller is compatible with the pci local bus specification , rev. 2.2. the pci interface is 32- bit compatible bus and capable of operating as either a host or an option (i.e., not the host) for more information on pci controller support and configuration see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual. 2.1.7 sdram controller the memory controller manages the interface to external sdram memory chips. the interface: ? operates at 133.32 mhz (which is 4 * osc_in input pin.) ? supports eight open pages simultaneously ? has two banks to support memory conf igurations from 8 mbyte to 256 mbyte the memory controller only supports 32-bit memory. if a x16 memory chip is used, a minimum of two memory chips would be required to facilit ate the 32-bit interface required by the ixp42x product line and ixc1100 control plane processors. a maximum of four sdram memory chips may be attached to the processors. for more information on sdram support and configuration see the intel ? ixp42x product line of network processors and ixc1100 control plane processor developer?s manual . the memory controller internally interfaces to the north ahb and south ahb with independent interfaces. this architecture allows sdram transfers to be interl eaved and pipelined to achieve maximum possible efficiency.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 24 document number: 252479, revision: 005 the maximum burst size supported to the sdram in terface is eight 32-bit words. this burst size allows the best efficiency/fai rness performance between accesses from the north ahb and the south ahb. 2.1.8 expansion bus the expansion interface allows eas y and ? in most cases ? glue-l ess connection to peripheral devices. it also provides input information for device configuration after reset. some of the peripheral device types are flas h, atm control interfaces, and ds ps used for voice applications. (some voice configurations can be supporte d by the hss interfaces and the intel xscale ? core, implementing voice-compression algorithms.) the expansion bus interface is a 16-bit interface th at allows an address range of 512 bytes to 16 mbytes, using 24 address lines for each of the eight indepe ndent chip selects. accesses to the expansion bus inte rface consists of five phases. e ach of the five phases can be lengthened or shortened by setting various configur ation registers on a per-chip-select basis. this feature allows the ixp42x product line and ixc1100 control plane processors to connect to a wide variety of peripheral devices with varying speeds. the expansion bus interface suppor ts intel or motorola* micropro cessor-style bus cycles. the bus cycles can be configured to be mu ltiplexed address/data cycles or separate address/data cycles for each of the eight chip-selects. additionally, chip selects 4 through 7 can be configured to support texas instruments hpi-8 or hpi-16 style accesses for dsps. the expansion bus interface is an asynchronous inte rface to externally conn ected chips. however, a clock must be supplied to the ixp42x product line and ixc1100 control plane processors? expansion bus interface for the interf ace to operate. this clock can be driven from gpio 15 or an external source. the maximum clock rate th at the expansion bus interface can accept is 66.66 mhz. at the de-assertion of reset, the 24-bit address bu s is used to capture co nfiguration information from the levels that are applied to the pins at this time. external pull-up/pull-down resistors are used to tie the signals to particular logic levels. (for additional details, see ?package and pinout information? on page 50 .) 2.1.9 high-speed, serial interfaces the high-speed, serial interfaces are six-signal interfaces that supp ort serial transfer speeds from 512 khz to 8.192 mhz, for some models of the ixp42x product line and ixc1100 control plane processors. (see table 4 on page 20 .) each interface allows direct connection of up to four t1/e1 framers and codec/slics to the ixp42x product line and ixc1100 control plane processors. the hi gh-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. for a list of supported protocols, see the intel ? ixp400 software programmer?s guide .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 25 2.1.10 high-speed and console uarts the uart interfaces ar e 16550-compliant uart s with the exception of transmit and receive buffers. transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 uart specification. the interface can be configured to support sp eeds from 1,200 baud to 921 kbaud. the interface support configurations of: ? five, six, seven, or eight data-bit transfers ? one or two stop bits ? even, odd, or no parity the request-to-send (rts_n) and clear-to-send (cts _n) modem control signal s also are available with the interface for hardware flow control. 2.1.11 gpio there are 16 gpio pins supported by the ixp42x product line and ixc1100 control plane processors. gpio pins 0 through 13 can be conf igured to be general-purpose input or general- purpose output. additionally, gpio pins 0 through 12 can be configured to be an interrupt input. gpio pin 14 can be configured similar to gpio pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33.33 mhz, with various duty cycles. gpio pin 14 is configured as an input, upon reset. gpio pin 15 can be configured similar to gpio pin 13 or as a clock output. the output-clock configuration can be set at various speeds, up to 33.33 mhz, with various duty cycles. gpio pin 15 is configured as a clock output, upon reset. gpio pin 15 can be used to clock the expansion interface, after reset. 2.1.12 internal bus performance monitoring unit (ibpmu) the ixp42x product line and ixc1100 control plane processors consists of seven 27-bit counters that may be used to capture predefined duratio ns or occurrence events on the north ahb, south ahb, or sdram controller page hits/misses. 2.1.13 interrupt controller the ixp42x product line and ixc1100 control plane processors consists of 32 interrupt sources to allow an extension of the intel xscale ? core fiq and irq interrupt sources. these sources can originate from some extern al gpio pins or intern al peripheral interfaces. the interrupt controller can conf igure each interrupt source as an fiq, irq, or disabled. the interrupt sources tied to interrupt 0 to 7 can be prioritized. the remaining interrupts are prioritized in ascending order. for example, interrupt 8 has a hi gher priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 26 document number: 252479, revision: 005 2.1.14 timers the ixp42x product line and ixc1100 control plane processors consists of four internal timers operating at 66.66 mhz (which is 2 * osc_in input pin.) to allow task scheduling and prevent software lock-ups. the device has four 32-bit counters: 2.1.15 ahb queue manager the ahb queue manager (aqm) provides queue functionality for various internal blocks. it maintains the queues as circular buffers in an em bedded 8kb sram. it also implements the status flags and pointers required for each queue. the aqm manages 64 independent queues. each queue is configurable for buffer and entry size. additionally status flags ar e maintained for each queue. the aqm interfaces include an advanced high- performance bus (ahb) interface to the npes and intel xscale core (or any other ahb bus master ), a flag bus interface, an event bus (to the npe condition select logic) and two interrupts to the intel xscale core. the ahb interface is used for configuration of th e aqm and provides access to queues, queue status and sram. individual queue status for queues 0-31 is communicated to the npes via the flag bu s. combined queue status for queues 32-63 are communicated to the npes via the event bus. the two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to the intel xscale core. 2.2 intel xscale ? core the intel xscale ? core technology is compliant with the arm * version 5te instruction-set architecture (isa). the inte l xscale core ? shown in figure 6 ? is designed with intel 0.18- production semiconductor process technology. this process technology enables the intel xscale core to operate over a wide speed and power range, producing industry-leading mw/mips performance. intel xscale core features include: ? seven/eight-stage super-pipeline promotes high-speed, efficient core performance ? 128-entry branch target buffer keeps pipeline f illed with statistically correct branch choices ? 32-entry instruction memory-management unit for logical-to-physical address translation, access permissions, i-cache attributes ? 32-entry data-memory manageme nt unit for logical-to-physical address translation, access permissions, d-cache attributes ? 32-kbyte instruction cache can hold entire programs, preven ting core stalls caused by multi- cycle memory accesses ? 32-kbyte data cache reduces core stalls caused by multi-cycle memory accesses ? 2-kbyte mini-data cache for frequ ently changing data streams avoids ?thrashing? of the d- cache ? four-entry fill-and-pend buffers to promote core efficiency by allowing ?hit-under-miss? operation with data caches ? watch-dog timer ? timestamp timer ? two general-purpose timers
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 27 ? eight-entry write buffer allows the core to cont inue execution while data is written to memory ? multiple-accumulate coprocessor that can do two simultaneous, 16 -bit, simd multiplies with 40-bit accumulation for efficient, hi gh-quality media an d signal processing ? performance monitoring unit (pmu) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. this pmu is for the intel xscale core only. an additional pmu is supplied for monitoring of internal bus performance. ? jtag debug unit that uses hardware break point s and 256-entry trace history buffer (for flow- change messages) to debug programs 2.2.1 super pipeline the super pipeline is composed of integer, multiply-accumulate (mac), and memory pipes. the integer pipe has seven stages: ? branch target buffer (btb)/fetch 1 ? fetch 2 ? decode ? register file/shift ? alu execute ? state execute ? integer writeback figure 6. intel xscale ? core block diagram a9568-02 multiply accumulate execution core interrupt request instruction fiq coprocessor interface irq data address data system management debug/ pmu jtag south ahb bus data cache 32 kb mini-data cache 2 kb m m u instruction cache 32 kb m m u branch target cache
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 28 document number: 252479, revision: 005 the memory pipe has eight stages: ? the first five stages of the integer pipe (btb/fetch 1 through alu execute) . . . then finish with the following memory stages: ? data cache 1 ? data cache 2 ? data cache writeback the mac pipe has six to nine stages: ? the first four stages of the integer pipe (btb/fetch 1 through register file/ shift) . . . then finish with the following mac stages: ? mac 1 ? mac 2 ? mac 3 ? mac 4 ? data cache writeback the mac pipe supports a data-dependent early terminate where stages mac 2, mac 3, and/or mac 4 are bypassed. deep pipes promote high instru ction execution rates only when a means exists to successfully predict the outcome of branch instructions. the branch target buffer provides such a means. 2.2.2 branch target buffer (btb) each entry of the 128-entry btb co ntains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. the history is recorded as one of four states: the btb can be enabled or disabled via coprocessor 15, register 1. when the address of the branch in struction hits in the btb and its history is strongly or weakly taken, the instruction at the branch target address is fetched. when its history is strongly or weakly not-taken, the next sequential instruction is fetched. in either case the history is updated. data associated with a branch instruction enters the btb the first time the branch is taken. this data enters the btb in a slot with a history of strongly not-taken (overwriting previous data when present). successfully predicted branches avoid any bran ch-latency penalties in the super pipeline. unsuccessfully predicted branches re sult in a four to five cycle br anch-latency penalty in the super pipeline. ? strongly taken ? weakly taken ? weakly not taken ? strongly not taken
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 29 2.2.3 instruction memory management unit (immu) for instruction pre-fetches, the immu controls logical-to-physical addre ss translation, memory access permissions, memory-domain identificati ons, and attributes (governing operation of the instruction cache). the immu contai ns a 32-entry, fully associativ e instruction-translation, look- aside buffer (itlb) that has a round-robin replacem ent policy. itlb entrie s zero through 30 can be locked. when an instruction pre-fetch misses in the it lb, the immu invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the itlb. the descriptor contains in formation for logical-to -physical address tran slation, memory-access permissions, memory-domain iden tifications, and attri butes governing operat ion of the i-cache. the immu then continues the inst ruction pre-fetch by using the a ddress translation just entered into the itlb. when an instruc tion pre-fetch hits in the itlb, the immu continues the pre-fetch using the address translation al ready resident in the itlb. access permissions for each of up to 16 memo ry domains can be pr ogrammed. when an instruction pre-fetch is attempte d to an area of memory in vi olation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 2.2.4 data memory management unit (dmmu) for data fetches, the dmmu controls logical -to-physical address tran slation, memory-access permissions, memory-domain iden tifications, and attributes (gov erning operation of the data cache or mini-data cache and write buffer). the dmmu contains a 32-entry, fully associative data- translation, look-aside buffer (d tlb) that has a round-robin repl acement policy. dtlb entries 0 through 30 can be locked. when a data fetch misses in the dtlb, the dmmu invokes an automatic table-walk mechanism that fetches an associated desc riptor from memory and loads it into the dtlb. the descriptor contains informatio n for logical-to-physical address translation, memory-access permissions, memory-domain identifications, an d attributes (governing operatio n of the d-cache or mini-data cache and write buffer). the dmmu continues the data fetch by using the a ddress translation just entered into the dtlb. when a data fetch hits in the dtlb, the dmmu continues the fetch using the address translation already resident in the dtlb. access permissions for each of up to 16 memory domains can be programmed. when a data fetch is attempted to an area of memo ry in violation of access permissi ons, the attempt is aborted and a data abort is sent to the core for exception processing. the immu and dmmu can be enabled or disabled together. 2.2.5 instruction cache (i-cache) the i-cache can contain high-use, multiple-code segments or enti re programs, allowing the core access to instructions at core frequencies. this prevents core stalls caused by multi-cycle accesses to external memory. the 32-kbyte i-cache is 32-set/32-wa y associative, where each set contains 32 ways and each way contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word), and a line-valid bit. for each of the 32 sets, 0 th rough 28 ways can be locked. unlocked ways are replaceable via a round-robin policy.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 30 document number: 252479, revision: 005 the i-cache can be enabled or disa bled. attribute bi ts within the descriptors ? contained in the itlb of the immu ? provide some control over an enabled i-cache. when a needed line (eight 32-bit wo rds) is not present in the i-cache, the line is fetched (critical word first) from memory via a two-level, deep -fetch queue. the fetch queue allows the next instruction to be accessed from the i-cache, but onl y when its data operands do not depend on the execution results of the instruction being fetched via the queue. 2.2.6 data cache (d-cache) the d-cache can contain high-use data such as looku p tables and filter coefficients, allowing the core access to data at core frequencies. this pr events core stalls caused by multi-cycle accesses to external memory. the 32-kbyte d-cache is 32-set/3 2-way associative, where each set contains 32 ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byt e groupings in a line), and one valid bit. for each of the 32 sets, zero through 28 ways can be locked, unlocked, or used as local sram. unlocked ways are replaceable via a round-robin policy. the d-cache (together with the mini-data cache) can be enabled or disabled. attribute bits within the descriptors, contained in the dtlb of the dmmu, provide significant control over an enabled d-cache. these bits specify cache operating modes su ch as read and write allocate, write-back, write-through, and d-cache vers us mini-data cache targeting. the d-cache (and mini-data cache) wo rk with the load bu ffer and pend buffer to provide ?hit- under-miss? capability that allows the core to access other data in the cache after a ?miss? is encountered. the d-cache (and mini -data cache) works in conjuncti on with the write buffer for data that is to be stored to memory. 2.2.7 mini-data cache the mini-data cache can contain fre quently changing data streams such as mpeg video, allowing the core access to data streams at core frequencies. this prevents core stalls caused by multi-cycle accesses to external memory. the mini-data cache relieves the d-cach e of data ?thrashing? caused by frequently changing data streams. the 2-kbyte, mini-data cache is 32 -set/two-way associative, where each set contains two ways and each way contains a tag address, a cache line (32 byt es with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line ), and a valid bit. the mini-data cache uses a round-robin replacement po licy, and cannot be locked. the mini-data cache (together with the d-cache) can be enabled or disabled. attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, write- back, and write-through. the mini-data cache (and d-cache) wo rk with the load bu ffer and pend buffer to provide ?hit- under-miss? capability that allows the core to access other data in the cache after a ?miss? is encountered. the mini-dat a cache (and d-cache) works in conjunc tion with the write buffer for data that is to be stored to memory.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 31 2.2.8 fill buffer (fb) and pend buffer (pb) the four-entry fill buffer (fb) works with the core to hold non-cacheable loads until the bus controller can act on them. the fb and the four-entry pend buffer (pb) work with the d-cache and mini-data cache to provide ?hit-under-miss? capability, allowing the core to seek other data in the caches while ?miss? data is being fetched from memory. the fb can contain up to four unique ?miss? addr esses (logical), allowing four ?misses? before the core is stalled. the pb holds up to four addresses (logical) for additional ?misses? to those addresses that are already in the fb. a coprocessor register can specify draining of the fill and pend (write) buffers. 2.2.9 write buffer (wb) the write buffer (wb) holds data for storage to memory until the bus controller can act on it. the wb is eight entries deep, where each entry hold s 16 bytes. the wb is co nstantly enabled and accepts data from the core , d-cache, or mini-data cache. coprocessor 15, register 1 specifies whether wb coalescing is enabled or disabled. when coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the dtlb. when coalescing is enab led, the attribute bits within the descriptors located in the dtlb are examined to determine when coales cing is enabled for the destination region of memory. when coalescing is enabled in both cp15, r1 and the dtlb, data entering the wb can coalesce with any of the ei ght entries (16 bytes) and be stored to the destination memory region, but possibly out of program order. stores to a memory region specified to be non- cacheable and non-bufferable by the attribute bits within the descriptors located in the dtlb causes the core to stall until the store completes. a coprocessor register can specify draining of the write buffer. 2.2.10 multiply-accumulate coprocessor (cp0) for efficient processing of hi gh-quality, media-and-signal-pro cessing algorithms, cp0 provides 40-bit accumulation of 16 x 16, dual-16 x 16 (simd), and 32 x 32 signed multiplies. special mar and mra instructions are impl emented to move the 40-bit accu mulator to two core-general registers (mar) and move two core -general registers to the 40-b it accumulator (mra). the 40-bit accumulator can be stored or loaded to or fr om d-cache, mini-data cache, or memory using two stc or ldc instructions. the 16 x 16 signed multiply-accumulates (miaxy) mu ltiply either the high/ high, low/low, high/ low, or low/high 16 bits of a 32-bit core genera l register (multiplier) and another 32-bit core general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-bit accumulator. dual-signed, 16 x 16 (simd) mu ltiply-accumulates (m iaph) multi ply the high/high and low/low 16-bits of a packed 32-bit, core -general register (multiplier) a nd another packed 32-bit, core- general register (multiplicand) to produce two 16-bits products that are both sign-extended to 40 bits and added to the 40-bit accumulator. the 32 x 32 signed multiply-accumulates (mia) multiply a 32-bit, core -general register (multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product where the 40 lsbs are added to the 40-bit accu mulator. the 16 x 32 versions of the 32 x 32 multiply-accumulate in structions complete in a single cycle.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 32 document number: 252479, revision: 005 2.2.11 performance monitoring unit (pmu) the performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter. the event counters can be program med to monitor i-cache hit rate, data caches hit rate, itlb hit rate, dtlb hit rate, pipeline stalls, btb predic tion hit rate, and instruction execution count. 2.2.12 debug unit the debug unit is accessed through the jtag port. the industry-standard, ieee 1149.1 jtag port consists of a test access port (tap) controller , boundary-scan register, instruction and data registers, and dedicated signals tdi, tdo, tck, tms, and trst#. the debug unit ? when used with debugger application code running on a host system outside of the intel xscale core ? allows a program, running on the intel xscale core, to be debugged. it allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine. debug exceptions are instruction breakpoint, data br eakpoint, software breakpoint, external debug breakpoint, exception vector trap , and trace buffer full breakpoint. once execution has stopped, the debugger application code can examine or modify the core?s state, coproc essor state, or memory. the debugger application code can then restart program execution. the debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint registers; and a hardware, data-br eakpoint control register. the sec ond data-breakpoint register can be alternatively used as a mask register for the first data-breakpoint register. a 256-entry trace buffer provides th e ability to capture control fl ow messages or addresses. a jtag instruction (ldic) can be used to download a debug handler via the jtag port to the mini- instruction cache (the i- cache has a 2-kbyte, mini-instructio n cache to hold a debug handler).
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 33 3.0 functional signal descriptions listed in the signal defini tion tables ? starting at table 6 ?sdram interface? on page 34 ? are pull-up an pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application. thes e external resistor requir ements are only needed if the particular model of intel ? ixp42x product line and ixc1100 control plane processors has the particular interface enabled and the interface is not re quired in the application. warning: all ixp42x product line and ixc1100 control plane processors i/o pins are not 5-v tolerant. disabled features, within the ixp42x product line and ixc1100 control plane processors, do not require external resistors as the processor will ha ve internal pull-up or pull-down resistors enabled as part of the disabled interface. table 5 presents the legend for interpreting the type field in the other tables in this section of the document. to determine which interfaces are not enabled within the ixp42x pr oduct line and ixc1100 control plane processors, see table 3 on page 14 . other tables in this section include: ? table 6 ? sdram interface signals ? table 7 ? pci controller signals table 5. signal type definitions symbol description i input pin only o output pin only i/o pin can be either an input or output od open drain pin pwr power pin gnd ground pin 1 driven to vcc 0 driven to vss x driven to unknown state id input is disabled h pulled up to vcc l pulled to vss pd pull-up disabled z output disabled vo a valid output level is driven, allowed states -- 1, 0, h, z vi need to drive a valid input level, allowed states - 1, 0, h, z pe pull-up enabled, equivalent to h tri output only/tristatable n/c no connect - pin must be connected as described
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 34 document number: 252479, revision: 005 ? table 8 ? high-speed, serial interface 0 signals ? table 9 ? high-speed, serial interface 1 signals ? table 10 ? mii interfaces signals ? table 11 ? utopia-2 interface signals ? table 12 ? expansion bus interface signals ? table 13 ? uart interfaces signals ? table 14 ? usb interface signals ? table 15 ? oscillator interface signals ? table 16 ? gpio interface signals ? table 17 ? jtag interface signals ? table 18 ? system interface?? signals ? table 19 ? power interface signals table 6. sdram interface (sheet 1 of 2) name power on reset 1 reset 2 type ? description sdm_addr[12:0] z 0 o sdram address: a0-a12 signals are output during the read/write commands and active commands to select a location in memory to act upon. sdm_data[31:0] z 1 i/o sdram data: bidirectional data bus used to transfer data to and from the sdram sdm_clkout z 0 o sdram clock: all sdram inpu t signals are sampled on the rising edge of sdm_clkout. all output signals are driven with respect to the rising edge of sdm_clkout. sdm_ba[1:0] z 0 o sdram bank address: sdm_ba0 and sdm_ba1 define the bank the current command is attempting to access. sdm_ras_n z 1 o sdram row address strobe/select (active low): along with sdm_cas_n, sdm_we_n, and sdm_cs_n signals determines the current command to be executed. sdm_cas_n z 1 o sdram column address strobe/select (active low): along with sdm_ras_n, sdm_we_n, and sdm_cs_n signals determines the current command to be executed. sdm_cs_n[1:0] z 1 o sdram chip select (active low): cs# enables the command decoder in the external sdram when logic low and disables the command decoder in the external sdram when logic high. sdm_we_n z 1 o sdram write enable (active low): along with sdm_cas_n, sdm_ras_n, and sdm_cs_n signals determines the current command to be executed. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 35 sdm_cke z 1 o sdram clock enable: cke is dr iving high to activate the clock to an external sdram and driven low to de-activate the clk to an external sdram. sdm_dqm[3:0] z 0 o sdram data bus mask: dqm is used to byte select data during read/write access to an external sdram. table 6. sdram interface (sheet 2 of 2) name power on reset 1 reset 2 type ? description 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 36 document number: 252479, revision: 005 table 7. pci controller (sheet 1 of 2) name power on reset 1 reset 2 type ? description pci_ad[31:0] z z i/o pci address/data bus used to transfer address and bidirectional data to and from multiple pci devices. should be pulled low with a 10-k ? resistor when not being utilized in the system. pci_cbe_n[3:0] z z i/o pci command/byte enables is used as a command word during pci address cycles and as byte enables for data cycles. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_par z z i/o pci parity used to check parity across the 32 bits of pci_ad and the four bits of pci_cbe_n. should be pulled low with a 10-k ? resistor when not being utilized in the system. pci_frame_n z z i/o pci cycle frame used to signify the beginning and duration of a transaction. the signal will be inacti ve prior to or during the final data phase of a given transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_trdy_n z z i/o pci target ready informs that the target of the pci bus is ready to complete the current data phase of a given transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_irdy_n z z i/o pci initiator ready informs the pci bus that the initiator is ready to complete the transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_stop_n z z i/o pci stop indicates that the current target is requesting the current initiator to stop the current transaction. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_perr_n z z i/o pci parity error asserted when a pci parity error is detected ? between the pci_par and associated information on the pci_ad bus and pci_cbe_n ? during all pci transactions, except for special cycles. the agent receiving data will drive this signal. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_serr_n z z i/od pci system error asserted when a parity error occurs on special cycles or any other error that will cause the pci bus not to function properly. this signal can function as an input or an open drain output. should be pulled high with a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 37 pci_devsel_n z z i/o pci device select: ? when used as an output, pci_devsel_n indicates that device has decoded that address as the target of the requested transaction. ? when used as an input, pci_d evsel_n indicates if any device on the pci bus exists with the given address. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_idsel z z i pci initialization device select is a chip select during configuration reads and writes. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_req_n[3:1] z z i pci arbitration request: used by the internal pci arbiter to allow an agent to request the pci bus. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_req_n[0] z z i/o pci arbitration request: ? when configured as an input (pci arbiter enabled), the internal pci arbiter will allow an agent to request the pci bus. ? when configured as an output (pci arbiter disabled), the pin will be used to request access to the pci bus from an external arbiter. should be pulled high with a 10-k ? resistor, when the pci bus is not being utilized in the system. pci_gnt_n[3:1] z z o pci arbitration grant: generated by the internal pci arbiter to allow an agent to claim control of the pci bus. pci_gnt_n[0] z z i/o pci arbitration grant: ? when configured as an output (pci arbiter enabled), the internal pci arbiter to allow an agent to claim control of the pci bus. ? when configured as an input (pci arbiter disabled), the pin will be used to claim access of the pci bus from an external arbiter. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_inta_n z z o/d pci interrupt: used to request an interrupt. should be pulled high with a 10-k ? resistor when not being utilized in the system. pci_clkin z vi i pci clock: provides timing for all transactions on pci. all pci signals ? except inta#, intb#, intc#, and intd# ? are sampled on the rising edge of clk and timing parameters are defined with respect to this edge. the pci clock rate can operate at up to 66 mhz. should be pulled low with a 10-k ? resistor when not being utilized in the system. table 7. pci controller (sheet 2 of 2) name power on reset 1 reset 2 type ? description 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and de assertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 38 document number: 252479, revision: 005 table 8. high-speed, serial interface 0 name power on reset 1 reset 2 type ? description hss_txframe0 z z i/o the high-speed serial (hss) transmit frame signal can be configured as an input or an output to allow an external source become synchronized with the transmitted data. often known as a frame sync signal . configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_txdata0 z z o/d transmit data out. open drain output. must be pulled high with a 10-k ? resistor to v ccp . hss_txclk0 z z i/o the high-speed serial (hss) tr ansmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxframe0 z z i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to become synchronized with the received data. often known as a frame sync signal . configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxdata0 z vi i receive data input. can be sampled on the rising or falling edge of the receive clock. should be pulled low through a 10-k ? resistor when not being utilized in the system. hss_rxclk0 z z i/o the high-speed serial (hss) receive clock signal can be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 39 table 9. high-speed, serial interface 1 name power on reset 1 reset 2 type ? description hss_txframe1 z z i/o the high-speed serial (hss) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized wi th the transmitted data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_txdata1 z z o/d transmit data out. open drain output. must be pulled high with a 10-k ? resistor to v ccp . hss_txclk1 z z i/o the high-speed serial (hss) tr ansmit clock signal can be configured as an input or an output. the clock can be a frequency ranging from 512 khz to 8.192 mhz. used to clock out the transmitted data. configured as an input upon reset. frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxframe1 z z i/o the high-speed serial (hss) receive frame signal can be configured as an input or an output to allow an external source to be synchronized wi th the received data. often known as a frame sync signal. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. hss_rxdata1 z vi i receive data input. can be sampled on the rising or falling edge of the receive clock. should be pulled low through a 10-k ? resistor when not being utilized in the system. hss_rxclk1 z z i/o the high-speed serial (hss) receive clock signal can be configured as an input or an output. the clock can be from 512 khz to 8.192 mhz. used to sample the received data. configured as an input upon reset. should be pulled low with a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 40 document number: 252479, revision: 005 table 10. mii interfaces (sheet 1 of 2) name power on reset 1 reset 2 type ? description eth_txclk0 z vi i externally suppli ed transmit clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_txdata0[3:0] z 0 o transmit data bus to phy, asserted synchronously with respect to eth_txclk0. eth_txen0 z 0 o indicates that the phy is being presented with nibbles on the mii interface. asserted sy nchronously, with respect to eth_txclk0, at the first nibble of the preamble and remains asserted until all the nibbles of a frame are presented. eth_rxclk0 z vi i externally suppli ed receive clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdata0[3:0] z vi i receive data bus from phy, data sampled synchronously with respect to eth_rxclk0 ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdv0 z vi i receive data valid, used to inform the mii interface that the ethernet phy is sending data. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_col0 z vi i asserted by the phy when a collision is detected by the phy. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_crs0 z vi i asserted by the phy when the transmit medium or receive medium is active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of a collision condition. phy asserts crs asynchronously and de-asserts synchronously, with respect to eth_rxclk0. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_mdio z z i/o management data output. provides the write data to both phy devices connected to each mii interface. an external 1.5-k ? pull-up resistor is required. note: if interfacing with a single intel ? lxt972 fast ethernet transceiver, and a 1.5k pull-up resistor is not used, the npe will ?see? 32 phys on the mii interface. should be pulled low through a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 41 eth_mdc z z o management data clock. management data interface clock is used to clock the mdio signal as an output and sample the mdio as an input. the eth_mdc is an input on power up and can be configured to be an output through an intel api as documented in the intel ? ixp400 software programmer?s guide . eth_txclk1 z vi i externally supplied transmit clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_txdata1[3:0] z 0 o transmit data bus to phy, asserted synchronously with respect to eth_txclk1. eth_txen1 z 0 o indicates that the phy is being presented with nibbles on the mii interface. asserted synchronously, with respect to eth_txclk1, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. eth_rxclk1 z vi i externally suppli ed receive clock. ? 25 mhz for 100 mbps operation ? 2.5 mhz for 10 mbps should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdata1[3:0] z vi i receive data bus from phy, data sampled synchronously, with respect to eth_rxclk1. ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_rxdv1 z vi i receive data valid, used to inform the mii interface that the ethernet phy is sending data. should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_col1 z vi i asserted by the phy when a co llision is detected by the phy. ? should be pulled low through a 10-k ? resistor when not being utilized in the system. eth_crs1 z vi i asserted by the phy when the transmit medium or receive medium are active. de-asserted when both the transmit and receive medium are idle. remains asserted throughout the duration of collision condition. phy asserts crs asynchronously and de-assert s synchronously with respect to eth_rxclk1. should be pulled low through a 10-k ? resistor when not being utilized in the system. table 10. mii interfaces (sheet 2 of 2) name power on reset 1 reset 2 type ? description 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 42 document number: 252479, revision: 005 table 11. utopia-2 interface (sheet 1 of 2) name power on reset 1 reset 2 type ? description utp_op_clk z vi i utopia transmit clock input. also known as utp_tx_clk. this signal is used to synchronize all utopia-transmit outputs to the rising edge of the utp_op_clk. this signal should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_op_fco z z o utopia flow control output signal. also known as the txenb_n signal. used to inform the selected phy that data is being transmitted to the phy. placing the phy?s address on the utp_op_addr ? and bringing utp_op_fco to logic 1, during the current clock ? followed by the utp_op_fco going to a logic 0, on the next clock cycle, selects which phy is active in mphy mode. in sphy configurations, utp_op_fco is used to inform the phy that the processor is ready to send data. utp_op_soc z z o start of cell. also known as tx_soc. active high signal is asserted when utp_op_data contains the first valid by te of a transmitted cell. utp_op_data[7:0] z z o utopia output data. also known as utp_tx_data. used to send data from the processor to an atm utopia- level-2-compliant phy. utp_op_addr[4:0] z vi o transmit phy address bus. used by the processor when operating in mphy mode to poll and select a single phy at any given time. utp_op_fci z vi i utopia output data flow control input: also known as the txfull/clav signal. used to inform the processor of the ability of each polled phy to receive a complete cell. for cell-level flow control in an mphy environment, txclav is an active high tri- stateable signal from the mphy to atm layer. the utp_op_fci, which is connected to multiple mphy devices, will see logic hi gh generated by the phy, one clock after the given phy address is asserted ? when a full cell can be received by the phy. the utp_op_fci will see a logic low generated by the phy one clock cycle, after the phy address is asserted ? if a full cell cannot be received by the phy. this signal should be tied low through a 10-k ? resistor if not being used. utp_ip_clk z vi i utopia receive clock input. also known as utp_rx_clk. this signal is used to synch ronize all utopia-received inputs to the rising edge of the utp_ip_clk. this signal should be pulled low through a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 43 utp_ip_fci z vi i utopia input data flow cont rol input signal. also known as rxempty/clav. used to inform the processor of the ability of each polled phy to send a complete cell. fo r cell-level flow control in an mphy environment, rxclav is an active high tri- stateable signal from the mphy to atm layer. the utp_ip_fci, which is connected to multiple mphy devices, will see logic high generated by the phy, one clock after the given phy addres s is asserted, when a full cell can be received by the phy. the utp_ip_fci will see a logic low generated by the phy, one clock cycle after the phy address is asserted if a full cell cannot be received by the phy. in sphy mode, this signal is used to indicate to the processor that the phy has an octet or cell available to be transferred to the processor . should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_soc z vi i start of cell. rx_soc active-high signal that is asserted when utp_ip_data contains the first valid by te of a transmitted cell. should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_data[7:0] z vi i utopia input data. also known as rx_data. used by to the processor to receive data from an atm utopia-level-2-compliant phy. should be pulled low through a 10-k ? resistor when not being utilized in the system. utp_ip_addr[4:0] z vi o receive phy address bus. used by the processor when operating in mphy mode to poll and select a single phy at any one given time. utp_ip_fco z z o utopia input data flow control output signal: also known as the rx_enb_n. in sphy configurations, utp_ ip_fco is used to inform the phy that the processor is ready to accept data. in mphy configurations, utp_ip_fco is used to select which phy will drive the utp_rx_data and utp_rx_soc signals. the phy is selected by placing the phy?s address on the utp_ip_addr and bringing utp_op_fco to logic 1 during the current clock, followed by the utp_op_fco going to a logic 0 on the next clock cycle. table 11. utopia-2 interface (sheet 2 of 2) name power on reset 1 reset 2 type ? description 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 44 document number: 252479, revision: 005 table 12. expansion bus interface name power on reset 1 reset 2 type ? description ex_clk z z i input clock signal used to samp le all expansion interface inputs and clock all expansion interface outputs. ex_ale z 0 o address-latch enable used for mu ltiplexed address/data bus accesses. used in intel and motorola* multiplexed modes of operation. ex_addr[23:0] h h i/o expansion-bus address used as an output for data accesses over the expansion bus. also, us ed as an input during reset to capture device configuration. these signals have a weak pull- up resistor attached internally. based on the desired configuration, various address signals must be tied low in order for the device to operate in the desired mode. ex_wr_n z 1 o intel-mode write strobe / motorola-mode data strobe (exp_mot_ds_n) / ti*-mode data strobe (ti_hds1_n). ex_rd_n z 1 o intel-mode read strobe / motorola-mode read-not-write (expb_mot_rnw) / ti mode read-not-write (ti_hr_w_n). ex_cs_n[7:0] z 1 o external chip selects for expansion bus. ? chip selects 0 through 7 can be configured to support intel or motorola bus cycles. ? chip selects 4 through 7 can be configured to support ti hpi bus cycles. ex_data[15:0] z 0 i/o expansion-bus, bidirectional data ex_iowait_n h h i data ready/acknowledge from expansion-bus devices. expansion-bus access is halte d when an external device sets ex_iowait_n to logic 0 and resume from the halted location once the external device sets ex_iowait_n to logic 1. this signal affects accesses that use ex_cs_n[7:0] when the chip select is configured in intel- or motorola-mode of operation. should be pulled high through a 10-k ? resistor when not being utilized in the system. ex_rdy[3:0] h h i hpi interface ready signals. c an be configured to be active high or active low. these si gnals are used to halt accesses using chip selects 7 through 4 when the chip selects are configured to operate in hpi mode. there is one rdy signal per chip select. this signal only affects accesses that use ex_cs_n[7:4]. should be pulled low though a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 45 table 13. uart interfaces name power on reset 1 reset 2 type ? description rxdata0 z vi i uart serial data input to high-speed uart pins. should be pulled low through a 10-k ? resistor when not being utilized in the system. txdata0 z vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. high-speed serial uart pins. cts0_n h vi/pe i uart clear-to-send input to high-speed uart pins. when logic 0, this pin indicates that the modem or data set connected to the uart interface of the processor is ready to exchange data. the cts_n signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts0_n h vo/pe o uart request-to-send output: when logic 0, this informs the modem or the data set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1). high-speed uart pins. rxdata1 z vi i uart serial data input. should be pulled low through a 10-k ? resistor when not being utilized in the system. txdata1 z vo o uart serial data output. the txd signal is set to the marking (logic 1) state upon a reset operation. console uart pins. cts1_n h vi/pe i uart clear-to-send input to console uart pins. when logic 0, this pin indicate s that the modem or data set connected to the uart interface of the processor is ready to exchange data. the cts_n signal is a modem status input whose condition can be tested by the processor. should be pulled high through a 10-k ? resistor when not being utilized in the system. rts1_n h vo/pe o uart request-to-send output: when logic 0, this informs the modem or the data set connected to the uart interface of the processor that the uart is ready to exchange data. a reset sets the request to send signal to logic 1. loop-mode operation holds this signal in its inactive state (logic 1). console uart pins. 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 46 document number: 252479, revision: 005 table 14. usb interface name power on reset 1 reset 2 type ? description usb_dpos z z i/o positive signal of the differential usb receiver/driver. usb_dneg z z i/o negative signal of the differential usb receiver/driver. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 . table 15. oscillator interface name power on reset 1 reset 2 type ? description osc_in i 33.33 mhz, sinusoidal crystal i nput signal. can be driven by an oscillator. osc_out o 33.33 mhz, sinusoidal crystal output signal. left disconnected when being driven by an oscillator. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 . table 16. gpio interface (sheet 1 of 2) name power on reset 1 reset 2 type ? description gpio[12:0] z z i/o general purpose input/output pins. may be configured as an input or an output. as an input, each signal may be configured a processor interrupt. default after reset is to be configured as inputs. should be pulled low using a 10-k ? resistor when not being utilized in the system. 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 47 gpio[13] z z i/o general purpose input/output pins. may be configured as an input or an output. default after reset is to be configured as inputs. should be pulled low using a 10-k ? resistor when not being utilized in the system. gpio[14] z z i/o can be configured similar to gpio pin 13 or as a clock output. configuration as an output clock c an be set at various speeds of up to 33.33 mhz with various duty cycles. configured as an input, upon reset. should be pulled low though a 10-k ? resistor when not being utilized in the system. gpio[15] z clkou t/vo i/o can be configured similar to gpio pin 13 or as a clock output. configuration as an output clock c an be set at various speeds of up to 33.33 mhz with various duty cycles. configured as an output, upon reset. can be used to clock the expansion interface, after reset. should be pulled low though a 10-k ? resistor when not being utilized in the system. table 17. jtag interface name power on reset 1 reset 2 type ? description jtg_tms h vi/pe i test mode select for the ieee 1149.1 jtag interface. jtg_tdi h vi/pe i input data for the ieee 1149.1 jtag interface. jtg_tdo z vo o output data for the ieee 1149.1 jtag interface. jtg_trst_n h vi/pe i used to reset the ieee 1149.1 jtag interface. the jtg_trst_n signal must be asserted (driven low) during power-up, otherwise the tap controller may not be initialized properly, and the processor may be locked. when the jtag interface is not being used, the signal must be pulled low using a 10-k ? resistor. jtg_tck z vi i used as the clock for the ieee 1149.1 jtag interface. 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 . table 16. gpio interface (sheet 2 of 2) name power on reset 1 reset 2 type ? description 1. while pwron_reset_n is deasserted use po wer on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the va lue shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 48 document number: 252479, revision: 005 table 18. system interface ?? name power on reset 1 reset 2 type ? description bypass_clk z vi i used for test purposes only. must be pulled high for normal operation. scantestmode_n h vi/pe i used for test purposes only. must be pulled high for normal operation. reset_in_n 0 vi i used as a reset input to the device after power up conditions have been met. powe r up conditions include the power supplies reaching a safe stable condition and the pll achieving a locked state and the pwron_reset_n coming to an active state prior to the reset_in_n coming to an active state. pwron_reset_n 0 vi i signal used at power up to reset all internal logic to a known state after the pll has achieved a locked state. the pwron_reset_n input is a 1.3-v tolerant only. highz_n h vi/pe i used for test purposes only. must be pulled high for normal operation. pll_lock z vo o signal used to inform external reset logic that the internal pll has achieved a locked state. rcomp i signal used to control pci dr ive strength characteristics. drive strength is varied on pci address, data and control signals. pin requires a 34- ? +/- 1% tolerance resistor to ground. refer to figure 13 on page 85 . 1. while pwron_reset_n is deasserted use power on reset column for the pin state. 2. after deassertion of pwron_reset_n, and deassertion of reset_in_n, and assertion of pll_lock, all signals reflect the value shown in the reset column. ? for a legend of the type codes, see table 5 on page 33 . ?? important note: when a system-level reset is asserted to the intel ? ixp42x product line of network processors and ixc1100 control plane proces sor ? either via a power-on reset, a system reset, or a watchdog-timer reset ? and any interface is in an active transaction (particularly the pci bus or expansion bus, but not prec luding any interface), an illegal pr otocol is generated. the behavior of the ixp42x product line and ixc1100 control plane pr ocessors is undefined in this situation and a reset of other attached devices may be required. table 19. power interface (sheet 1 of 2) name type ? description vcc i 1.3-v power supply input pins used for the internal logic. vccp i 3.3-v power supply input pins used for the peripheral (i/o) logic. vss ground power supply input pins used for both the 3.3-v and the 1.3-v power supplies. vccoscp i 3.3-v power supply input pins used for th e peripheral (i/o) logic of the analog oscillator circuitry. require special power filter ing circuitry. refer to figure 11 on page 84 vssoscp i ground input pins used for the peripheral (i/o ) logic of the analog o scillator circuitry. used in conjunction with the vccoscp pins. requires special power filtering circuitry. refer to figure 11 on page 84 ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 49 vccosc i 1.3-v power supply input pins used for the in ternal logic of the analog oscillator circuitry. requires special power filt ering circuitry. refer to figure 12 on page 84 vssosc i ground power supply input pins used for the internal logic of the analog oscillator circuitry. used in conjunct ion with the vccosc pins. requires special power filt ering circuitry. refer to figure 12 on page 84 vccpll1 i 1.3-v power supply input pins used for the internal logic of t he analog phase lock-loop circuitry. requires special power filt ering circuitry. refer to figure 9 on page 83 vccpll2 i 1.3-v power supply input pins used for the internal logic of t he analog phase lock-loop circuitry. requires special power filt ering circuitry. refer to figure 10 on page 83 table 19. power interface (sheet 2 of 2) name type ? description ? for a legend of the type codes, see table 5 on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 50 document number: 252479, revision: 005 4.0 package and pinout information the intel ? ixp42x product line of network processors and ixc1100 control plane processor have a 492-ball, plastic ball grid array (pbga) package for commercial-tem perature applications and a pin-for-pin, compatible 492-b all, plastic ball grid array with a drop-in heat spreader (h) for extended-temperature applications. 4.1 package description figure 7. 492-pin lead pbga package 1. all measurements are in millimeters (mm). 2. the size of the land pad at the interposer side (1) is 0.81 mm. 3. the size of the solder resist at the interposer side (2) is 0.66 mm. b1268-03 0.60 0.10 seating plane 30o 3 1.17 0.05 2.38 0.21 0.61 0.06 0.15 c 0.20 -c- side view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r aa y w u t 23 22 21 20 19 18 17 16 24 25 26 v ab ac ad ae af pin #1 corner 1.27 1.63 ref 1.27 a c ? 0.30 b s ?1.0 3 places 2 + + 1.63 ref 0.90 0.60 ? s s + + + 22.00 ref 22.00 ref 35.00 0.20 35.00 0.20 30.00 0.25 pin 1 id 30.00 0.25 45o chamfer 4 places 0.127 a -b- -a- top view (1) (2)
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 51 figure 8. package markings note: see table 20 for specific on ?level 1 name.? table 20. part numbers (sheet 1 of 2) device stepping speed (mhz) part # intel ? ixp425 network processor b-0 533 fwixp425bd intel ? ixp425 network processor b-0 400 fwixp425bc intel ? ixp425 network processor b-0 266 fwixp425bb intel ? ixp425 network processor b-0 533 extended temperature gwixp425bdt intel ? ixp425 network processor b-0 400 extended temperature gwixp425bct intel ? ixp425 network processor b-0 266 extended temperature gwixp425bbt intel ? ixp423 network processor b-0 266 fwixp423bb intel ? ixp422 network processor b-0 266 fwixp422bb intel ? ixp421 network processor b-0 266 fwixp421bb bsmc (atpo#, date code and coo) pin #1 (not a mark) i fwixp42 xbx intel m c 2002 level 1 name yww korea bsmc marking zone: 0.380? max. *
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 52 document number: 252479, revision: 005 intel ? ixp420 network processor b-0 533 fwixp420bd intel ? ixp420 network processor b-0 400 FWIXP420BC intel ? ixp420 network processor b-0 266 fwixp420bb intel ? ixp420 network processor b-0 266 extended temperature gwixp420bbt intel ? ixc1100 control plane processor b-0 533 fwixc1100bd intel ? ixc1100 control plane processor b-0 400 fwixc1100bc intel ? ixc1100 control plane processor b-0 266 fwixc1100bb intel ? ixc1100 control plane processor b-0 533 extended temperature gwixc1100bdt intel ? ixc1100 control plane processor b-0 400 extended temperature gwixc1100bct intel ? ixc1100 control plane processor b-0 266 extended temperature gwixc1100bbt table 20. part numbers (sheet 2 of 2) device stepping speed (mhz) part #
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 53 4.2 signal-pin descriptions in this section, separate ball -map-assignment tables are give n for each model of the ixp42x product line and ixc1100 control plan e processors. these tables include: device table # starting page intel ? ixp425 network processor 21 53 intel ? ixp423 network processor 21 53 intel ? ixp422 network processor 22 60 intel ? ixp421 network processor 23 67 intel ? ixp420 network processor and intel ? ixc1100 control plane processor 24 74 table 21. ball map assignment for the intel ? ixp425 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 54 document number: 252479, revision: 005 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 21. ball map assignment for the intel ? ixp425 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 55 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 21. ball map assignment for the intel ? ixp425 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 56 document number: 252479, revision: 005 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 21. ball map assignment for the intel ? ixp425 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 57 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 hss_txclk0 u2 vccp v2 vss w2 vccp y2 hss_rxclk0 u3 pci_ad[0] v3 pci_ad[3] w3 hss_rxframe0 y3 hss_txframe1 u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 hss_txdata0 v5 hss_txfr ame0 w5 hss_txclk1 y5 vccp u6 vcc v6 vss w6 hss_rxframe1 y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 21. ball map assignment for the intel ? ixp425 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 58 document number: 252479, revision: 005 aa1 hss_rxdata0 ab1 hss_txdata1 ac1 vss ad1 eth_txclk0 aa2 vccp ab2 hss_rxdata1 ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 hss_rxclk1 ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 utp_op_data[7] ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 utp_op_data[4] ab15 utp_op_soc ac15 utp_op_data[1] ad15 utp_op_data[2] ab16 vss ac16 utp_op_fci ad16 vss aa17 vcc ab17 utp_ip_data[6] ac17 utp_op_addr[1] ad17 utp_op_addr[3] aa18 utp_ip_fci ab18 vccp ac18 vcc ad18 utp_ip_data[7] aa19 utp_ip_addr[0] ab19 utp_ip_clk ac19 utp_ip_data[2] ad19 vccp aa20 vss ab20 utp_ip_addr[1] ac20 utp_ip_soc ad20 utp_ip_data[1] aa21 vcc ab21 scantestmode_n ac21 vcc ad21 utp_ip_addr[4] aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 21. ball map assignment for the intel ? ixp425 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 59 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 utp_op_data[5] af14 utp_op_data[6] ae15 vss af15 utp_op_data[3] ae16 utp_op_fco af16 utp_op_data[0] ae17 vccp af17 utp_op_clk ae18 utp_op_addr[2] af18 utp_op_addr[4] ae19 vss af19 utp_op_addr[0] ae20 utp_ip_data[4] af20 utp_ip_data[5] ae21 vccp af21 utp_ip_data[3] ae22 utp_ip_fco af22 utp_ip_data[0] ae23 vccp af23 utp_ip_addr[3] ae24 jtg_tdi af24 utp_ip_addr[2] ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 21. ball map assignment for the intel ? ixp425 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 60 document number: 252479, revision: 005 table 22. ball map assignment for the intel ? ixp422 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 61 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 22. ball map assignment for the intel ? ixp422 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 62 document number: 252479, revision: 005 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 22. ball map assignment for the intel ? ixp422 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 63 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 22. ball map assignment for the intel ? ixp422 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 64 document number: 252479, revision: 005 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 n/c u2 vccp v2 vss w2 vccp y2 n/c u3 pci_ad[0] v3 pci_ad[3] w3 n/c y3 n/c u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 n/c v5 n/c w5 n/c y5 vccp u6 vcc v6 vss w6 n/c y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 22. ball map assignment for the intel ? ixp422 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 65 aa1 n/c ab1 n/c ac1 vss ad1 eth_txclk0 aa2 vccp ab2 n/c ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 n/c ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 v ss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 n/c ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 n/c ab15 n/c ac15 n/c ad15 n/c ab16 vss ac16 n/c ad16 vss aa17 vcc ab17 n/c ac17 n/c ad17 n/c aa18 n/c ab18 vccp ac18 vcc ad18 n/c aa19 n/c ab19 n/c ac19 n/c ad19 vccp aa20 vss ab20 n/c ac20 n/c ad20 n/c aa21 vcc ab21 scantestmode_n ac21 vcc ad21 n/c aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 22. ball map assignment for the intel ? ixp422 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 66 document number: 252479, revision: 005 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 n/c af14 n/c ae15 vss af15 n/c ae16 n/c af16 n/c ae17 vccp af17 n/c ae18 n/c af18 n/c ae19 vss af19 n/c ae20 n/c af20 n/c ae21 vccp af21 n/c ae22 n/c af22 n/c ae23 vccp af23 n/c ae24 jtg_tdi af24 n/c ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 22. ball map assignment for the intel ? ixp422 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 67 table 23. ball map assignment for the intel ? ixp421 network processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 68 document number: 252479, revision: 005 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 23. ball map assignment for the intel ? ixp421 network processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 69 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 23. ball map assignment for the intel ? ixp421 network processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 70 document number: 252479, revision: 005 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 23. ball map assignment for the intel ? ixp421 network processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 71 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 hss_txclk0 u2 vccp v2 vss w2 vccp y2 hss_rxclk0 u3 pci_ad[0] v3 pci_ad[3] w3 hss_rxframe0 y3 hss_txframe1 u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 hss_txdata0 v5 hss_txfr ame0 w5 hss_txclk1 y5 vccp u6 vcc v6 vss w6 hss_rxframe1 y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 23. ball map assignment for the intel ? ixp421 network processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 72 document number: 252479, revision: 005 aa1 hss_rxdata0 ab1 hss_txdata1 ac1 vss ad1 eth_txclk0 aa2 vccp ab2 hss_rxdata1 ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 hss_rxclk1 ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 vss ad6 n/c aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 n/c aa8 vss ab8 n/c ac8 n/c ad8 n/c aa9 n/c ab9 n/c ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 utp_op_data[7] ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 utp_op_data[4] ab15 utp_op_soc ac15 utp_op_data[1] ad15 utp_op_data[2] ab16 vss ac16 utp_op_fci ad16 vss aa17 vcc ab17 utp_ip_data[6] ac17 utp_op_addr[1] ad17 utp_op_addr[3] aa18 utp_ip_fci ab18 vccp ac18 vcc ad18 utp_ip_data[7] aa19 utp_ip_addr[0] ab19 utp_ip_clk ac19 utp_ip_data[2] ad19 vccp aa20 vss ab20 utp_ip_addr[1] ac20 utp_ip_soc ad20 utp_ip_data[1] aa21 vcc ab21 scantestmode_n ac21 vcc ad21 utp_ip_addr[4] aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 23. ball map assignment for the intel ? ixp421 network processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 73 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 n/c af4 n/c ae5 vccp af5 n/c ae6 n/c af6 n/c ae7 vss af7 n/c ae8 n/c af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 utp_op_data[5] af14 utp_op_data[6] ae15 vss af15 utp_op_data[3] ae16 utp_op_fco af16 utp_op_data[0] ae17 vccp af17 utp_op_clk ae18 utp_op_addr[2] af18 utp_op_addr[4] ae19 vss af19 utp_op_addr[0] ae20 utp_ip_data[4] af20 utp_ip_data[5] ae21 vccp af21 utp_ip_data[3] ae22 utp_ip_fco af22 utp_ip_data[0] ae23 vccp af23 utp_ip_addr[3] ae24 jtg_tdi af24 utp_ip_addr[2] ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 23. ball map assignment for the intel ? ixp421 network processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 74 document number: 252479, revision: 005 table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 1 of 7) ball signal ball signal ball signal ball signal a1 pci_ad[27] b1 pci_ad[28] c1 pci_ad[26] d1 pci_ad[25] a2 pci_gnt_n[1] b2 vccp c2 pci_ad[30] d2 vss a3 pci_gnt_n[3] b3 pci_gnt_n[2] c3 vss d3 pci_ad[31] a4 sdm_data[19] b4 vccp c4 pci_inta_n d4 vcc a5 sdm_data[27] b5 sdm_data[28] c5 vss d5 pci_serr_n a6 sdm_data[26] b6 vccp c6 sdm_data[18] d6 vcc a7 sdm_data[25] b7 sdm_data[21] c7 vss d7 sdm_data[29] a8 sdm_data[23] b8 vss c8 vccp d8 sdm_data[20] a9 sdm_data[14] b9 sdm_data[0] c9 sdm_data[24] d9 vcc a10 sdm_data[13] b10 vccp c10 vss d10 sdm_data[15] a11 sdm_data[11] b11 sdm_data[12] c11 sdm_data[2] d11 sdm_data[1] a12 sdm_data[10] b12 vss c12 sdm_data[4] d12 vcc a13 sdm_data[6] b13 sdm_data[9] c13 vss d13 sdm_data[5] a14 sdm_data[8] b14 vccp c14 sdm_data[7] d14 vcc a15 sdm_dqm[1] b15 sdm_dqm[2] c15 sdm_dqm[3] d15 sdm_we_n a16 sdm_cs_n[0] b16 vss c16 vccp d16 sdm_cs_n[1] a17 sdm_clkout b17 sdm_cke c17 sdm_cas_n d17 sdm_ba[1] a18 sdm_ras_n b18 vccp c18 sdm_addr[11] d18 vcc a19 sdm_addr[12] b19 sdm_addr[10] c19 vss d19 sdm_addr[0] a20 sdm_addr[9] b20 vss c20 sdm_addr[6] d20 vss a21 sdm_addr[8] b21 sdm_addr[1] c21 sdm_addr[2] d21 vcc a22 sdm_addr[5] b22 vccp c22 vss d22 ex_ale a23 ex_rd_n b23 ex_iowait_n c23 ex_addr[0] d23 vcc a24 ex_addr[1] b24 vss c24 ex_addr[4] d24 ex_addr[6] a25 ex_addr[3] b25 vccp c25 ex_addr[7] d25 rcomp a26 ex_addr[5] b26 ex_addr[9] c26 ex_addr[13] d26 ex_addr[17] note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 75 e1 pci_ad[23] f1 pci_ad[20] g1 pci_ad[21] h1 pci_ad[16] e2 vccp f2 pci_idsel g2 vccp h2 pci_ad[18] e3 pci_req_n[2] f3 vcc g3 pci_ad[24] h3 vcc e4 vss f4 pci_req_n[0] g4 vss h4 pci_cbe_n[3] e5 pci_gnt_n[0] f5 vccp g5 pci_req_n[1] h5 vcc e6 sdm_data[16] f6 vcc g6 vss h6 pci_req_n[3] e7 vccp f7 sdm_data[31] e8 sdm_data[30] f8 vss e9 vss f9 sdm_data[17] e10 sdm_data[22] f10 vcc e11 vccp e12 sdm_data[3] e13 vss e14 sdm_dqm[0] e15 vccp e16 sdm_ba[0] e17 vss f17 vcc e18 sdm_addr[7] f18 sdm_addr[4] e19 vccp f19 vss e20 sdm_addr[3] f20 usb_dpos e21 usb_dneg f21 vcc g21 ex_addr[2] h21 vss e22 vccp f22 ex_wr_n g22 vss h22 ex_addr[11] e23 vss f23 vcc g23 ex_addr[12] h23 ex_addr[18] e24 ex_addr[10] f24 ex_addr[14] g24 vss h24 vccp e25 ex_addr[15] f25 vccp g25 ex_addr[20] h25 vss e26 ex_addr[19] f26 ex_addr[21] g26 ex_addr[22] h26 ex_cs_n[1] table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 2 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 76 document number: 252479, revision: 005 j1 pci_clkin k1 pci_cbe_n[2] l1 pci_devsel_n m1 pci_cbe_n[1] j2 vccp k2 vss l2 vccp m2 pci_par j3 vss k3 pci_ad[17] l3 pci_stop_n m3 vss j4 pci_ad[22] k4 vccp l4 vcc m4 pci_irdy_n j5 vss k5 pci_ad[19] l5 pci_frame_n m5 vccp j6 pci_ad[29] k6 vcc l11 vss m11 vss l12 vss m12 vss l13 vss m13 vss l14 vss m14 vss l15 vss m15 vss l16 vss m16 vss j21 ex_addr[8] k21 vcc j22 ex_addr[16] k22 vss l22 vccp m22 ex_cs_n[5] j23 vcc k23 ex_cs_n[0] l23 vcc m23 ex_clk j24 ex_addr[23] k24 ex_cs_n[3] l24 ex_cs_n[6] m24 ex_data[2] j25 ex_cs_n[2] k25 vccp l25 ex_data[0] m25 vss j26 ex_cs_n[4] k26 ex_cs_n[7] l26 ex_data[1] m26 ex_data[3] table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 3 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 77 n1 pci_ad[11] p1 pci_cbe_n[0] r1 pci_ad[10] t1 pci_ad[6] n2 vccp p2 pci_ad[14] r2 vss t2 pci_trdy_n n3 vcc p3 pci_ad[13] r3 pci_ad[9] t3 vss n4 pci_perr_n p4 vss r4 vcc t4 pci_ad[2] n5 pci_ad[15] p5 pci_ad[12] r5 pci_ad[4] t5 vccp n11 vss p11 vss r11 vss t11 vss n12 vss p12 vss r12 vss t12 vss n13 vss p13 vss r13 vss t13 vss n14 vss p14 vss r14 vss t14 vss n15 vss p15 vss r15 vss t15 vss n16 vss p16 vss r16 vss t16 vss n22 vcc p22 ex_data[6] r22 vccp t22 ex_rdy_n[0] n23 vss p23 ex_data[7] r23 vcc t23 vss n24 vcc p24 ex_data[8] r24 ex_data[12] t24 ex_data[14] n25 ex_data[4] p25 vccp r25 ex_data[11] t25 vss n26 ex_data[5] p26 ex_data[9] r26 ex_data[10] t26 ex_data[13] table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 4 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 78 document number: 252479, revision: 005 u1 pci_ad[8] v1 pci_ad[5] w1 pci_ad[1] y1 n/c u2 vccp v2 vss w2 vccp y2 n/c u3 pci_ad[0] v3 pci_ad[3] w3 n/c y3 n/c u4 pci_ad[7] v4 vcc w4 vss y4 vcc u5 n/c v5 n/c w5 n/c y5 vccp u6 vcc v6 vss w6 n/c y6 eth_txen0 u21 vcc v21 gpio[6] w21 gpio[1] y21 rxdata1 u22 gpio[14] v22 gpio[9] w22 vccp y22 gpio[0] u23 ex_rdy_n[1] v23 vcc w23 gpio[8] y23 vcc u24 ex_rdy_n[2] v24 gpio[13] w24 vss y24 gpio[5] u25 gpio[15] v25 vccp w25 gpio[11] y25 vccp u26 ex_data[15] v26 ex_rdy_n[3] w26 gpio[12] y26 gpio[10] table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 5 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 79 aa1 n/c ab1 n/c ac1 vss ad1 eth_txclk0 aa2 vccp ab2 n/c ac2 eth_txdata0[0] ad2 eth_rxdv0 aa3 vss ab3 eth_txdata0[3] ac3 vccp ad3 vss aa4 n/c ab4 eth_txdata0[1] ac4 vcc ad4 eth_crs0 aa5 eth_txdata0[2] ab5 vss ac5 eth_rxdata0[0] ad5 eth_mdc aa6 vcc ab6 eth_rxclk0 ac6 v ss ad6 eth_txdata1[0] aa7 eth_rxdata0[1] ab7 vccp ac7 vcc ad7 eth_rxdata1[3] aa8 vss ab8 eth_txdata1[2] ac8 eth_rxdata1[2] ad8 eth_rxclk1 aa9 eth_txdata1[1] ab9 eth_rxdata1[1] ac9 vcc ad9 vss aa10 vcc ab10 vccp ac10 vcc ad10 vssoscp ab11 vccp ac11 vccoscp ad11 vccp ab12 vss ac12 vcc ad12 pll_lock ab13 n/c ac13 reset_in_n ad13 pwron_reset_n ab14 vccp ac14 vcc ad14 n/c ab15 n/c ac15 n/c ad15 n/c ab16 vss ac16 n/c ad16 vss aa17 vcc ab17 n/c ac17 n/c ad17 n/c aa18 n/c ab18 vccp ac18 vcc ad18 n/c aa19 n/c ab19 n/c ac19 n/c ad19 vccp aa20 vss ab20 n/c ac20 n/c ad20 n/c aa21 vcc ab21 scantestmode_n ac21 vcc ad21 n/c aa22 txdata1 ab22 vccp ac22 jtg_trst_n ad22 vss aa23 vss ab23 cts0_n ac23 vcc ad23 jtg_tdo aa24 gpio[3] ab24 cts1_n ac24 rxdata0 ad24 vss aa25 vss ab25 vccp ac25 rts1_n ad25 txdata0 aa26 gpio[7] ab26 gpio[4] ac26 gpio[2] ad26 rts0_n table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 6 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utilized at a system level require exter nal pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 80 document number: 252479, revision: 005 ae1 eth_rxdata0[3] af1 eth_rxdata0[2] ae2 vccp af2 eth_mdio ae3 eth_col0 af3 (reserved) ae4 eth_txen1 af4 eth_txdata1[3] ae5 vccp af5 eth_txclk1 ae6 eth_rxdv1 af6 eth_rxdata1[0] ae7 vss af7 eth_crs1 ae8 eth_col1 af8 vssosc ae9 vccp af9 osc_in ae10 vccpll1 af10 vssoscp ae11 vss af11 osc_out ae12 vccpll2 af12 vccosc ae13 vccp af13 bypass_clk ae14 n/c af14 n/c ae15 vss af15 n/c ae16 n/c af16 n/c ae17 vccp af17 n/c ae18 n/c af18 n/c ae19 vss af19 n/c ae20 n/c af20 n/c ae21 vccp af21 n/c ae22 n/c af22 n/c ae23 vccp af23 n/c ae24 jtg_tdi af24 n/c ae25 vccp af25 jtg_tms ae26 highz_n af26 jtg_tck table 24. ball map assignment for the intel ? ixp420 network processor and intel ? ixc1100 control plane processor (sheet 7 of 7) ball signal ball signal ball signal ball signal note: interfaces not being utiliz ed at a system level require external pull-up or pull-down resistors. for specific details and requirements, see section 3.0, ?functional signal descriptions? on page 33 .
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 81 4.3 package thermal specifications the thermal characterization parameter ? jt? is proportional to the temperature difference between the top, center of the pack age and the junction temperature. this can be a useful value fo r verifying device temperatures in an actual environment. by measuring the package of the device, the junction temperature can be estimated, if the thermal characterization parameter has been measured under similar conditions. the use of jt should not be confused with jc, which is the thermal resistance from the device junction to the external surface of the package or case nearest the die attachment ? as the case is held at a constant temperature. the case temperature can then be monitored to ma ke sure that the maximum junction temperature is not violated. examples are gi ven in the following sections. note: for more information on jt, refer to the eia/jedec standard 51-2, section 4. 4.3.1 commercial temperature ?commercial? temperature range is defined in te rms of the ambient temper ature range, which is specified as 0 c to 70 c. the maximum power (p) is 2.4 w and the maximum junction temperature (t j ) is 115 c. jt for commercial temperature is 0.89 c/w. using the preceding junction-temp erature formula, the commerci al temperature for a 266 mhz device ? assuming a maximum power of 2 w ? would be: 4.3.2 extended temperature ?extended? temperature range is defined in terms of the ambient temperature range, which is specified as -40 c to 85 c. the maximum power (p) is 2.4 w and the maximum junction temperature (t j ) is 115 c. jt for extended temperature is 0.32 c/w. using the preceding junction-temper ature formula, the extended te mperature for a 533 mhz device ? assuming a maximum power of 2.4 w ? would be: case temperature = junction temperature - ( jt * power dissipation) t jc = t j - ( jt * power dissipation) t jc = 115 c - (0.89 * 2.0) t jc = 113.22 c t jc = 115 c - (0.32 * 2.4) t jc = 114.23 c
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 82 document number: 252479, revision: 005 5.0 electrical specifications 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. 5.2 v ccpll1 , v ccpll2 , v ccoscp , v ccosc pin requirements to reduce voltage-supply noise on the analog sections of the intel ? ixp42x product line of network processors and ixc1100 control plane processor, the phase-lo ck loop circuits (v ccpll1 , v ccpll2 ) and oscillator circuit (v ccoscp , v ccosc ) require isolated voltage supplies. the filter circuits for each supply ar e shown in the following sections. 5.2.1 v ccpll1 requirement a parallel combination of a 10-nf capacitor ? fo r bypass ? and a 200-nf capacitor ? for a first- order filter with a cut-off frequency below 30 mhz ? must be connected to the v ccpll1 pin of the intel ? ixp42x product line and ixc1100 control plane processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll1 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a para llel combination of two 100-nf capacitors may be used as long as the capacitors ar e placed directly beside each other. parameter maximum rating ambient air temperature (extended) -40o c to 85o c ambient air temperature (commercial) 0o c to 70o c supply voltage core -0.3 v to 2.1v supply voltage i/o -0.3 v to 3.6v supply voltage oscillator (v ccosc ) -0.3 v to 2.1v supply voltage oscillator (v ccoscp ) -0.3 v to 3.6v supply voltage pll (v ccpll1 ) -0.3 v to 2.1v supply voltage pll (v ccpll2 ) -0.3 v to 2.1v voltage on any i/o ball -0.3 v to 3.6v storage temperature -55 o c to 125 o c
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 83 5.2.2 v ccpll2 requirement a parallel combination of a 10 -nf capacitor ? for bypass ? and a 200-nf capacitor ? for a first- order filter with a cut-off frequency be low 30 mhz ? must be connected to the v ccpll2 pin of the ixp42x product line and ixc1100 control plane processors. the ground of both capacitors should be connected to the nearest v ss supply pin. both capacitors should be located less than 0.5 inch away from the v ccpll2 pin and the associated v ss pin. in order to achieve the 200-nf capacitance, a parall el combination of two 100-nf capacitors may be used as long as the capacitors are placed directly beside each other. 5.2.3 v ccoscp requirement a single 170-nf capacitor must be connected between the v ccp_osc pin and v ssp_osc pin of the ixp42x product line and ixc1100 control plane processors. this capacitor value provides both bypass and filtering. figure 9. v ccpll1 power filtering diagram 1.3 v intel ? ixp42x product line / intel ? ixc1100 control plane processor 10 nf v ss v ccpll1 100 nf 100 nf v ss b1680-03 figure 10. v ccpll2 power filtering diagram intel ? ixp42x product line / intel ? ixc1100 control plane processor 1.3 v 10 nf v ss v ccpll2 100 nf 100 nf v ss b1681-03
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 84 document number: 252479, revision: 005 when 170 nf is an inconvenient size, capacitor values between 150 nf to 200 nf could be used with little adverse effects, assu ming that the effective series re sistance of the 200-nf capacitor is under 50 m ? . in order to achieve a 200-nf cap acitance, a parallel combination of two 100-nf capacitors may be used as long as the cap acitors are placed directly beside each other. v ssp_osc consists of two pins, ad10 and af10. ensure that both pins are connected as shown in figure 11 . 5.2.4 v ccosc requirement a parallel combination of a 10-nf capacitor ? fo r bypass ? and a 200-nf capacitor ? for a first- order filter with a cut-off frequency below 33 mhz ? must be connected to both of the v ccosc pins of the ixp42x product line and ixc1100 control plane processors. the grounds of both capacitors should be connected to the v ssosc supply pin. both capacitors should be located less than 0.5 inch away from the v ccosc pin and the associated v ssosc pin. in order to achieve a 200-nf cap acitance, a parallel combination of two 100-nf capacitors may be used as long as the capacitors ar e placed directly beside each other. figure 11. v ccoscp power filtering diagram intel ? ixp42x product line / intel ? ixc1100 control plane processor 3.3 v 170 nf v ss v ccoscp v ssoscp v ssoscp b1675-04 figure 12. v ccosc power filtering diagram intel ? ixp42x product line / intel ? ixc1100 control plane processor 1.3 v 10 nf v ss 100 nf 100 nf b1676-03
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 85 5.3 rcomp pin requirements figure 13 shows the requiremen ts for the rcomp pin. 5.4 dc specifications 5.4.1 operating conditions figure 13. rcomp pin external resistor requirements table 25. operating conditions symbol parameter min. typ. max. units notes v ccp voltage supplied to the i/o. 3.135 3.3 3.465 v v cc voltage supplied to the internal logic. 1.235 1.3 1.365 v v ccosc voltage supplied to the internal oscillator logic. 1.235 1.3 1.365 v v ccoscp voltage supplied to the oscillator i/o. 3.135 3.3 3.465 v v ccpll1 voltage supplied to the analog phase-lock loop. 1.235 1.3 1.365 v v ccpll2 voltage supplied to the analog phase-lock loop. 1.235 1.3 1.365 v intel ? ixp42x product line / intel ? ixc1100 control plane processor v ss rcomp v ss 34 , + 1% b1672-02
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 86 document number: 252479, revision: 005 5.4.2 pci dc parameters 5.4.3 usb dc parameters table 26. pci dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 0.5 v ccp v 4 v il input-low voltage 0.3 v ccp v 3 v oh output-high voltage i out = -500 a 0.9 v ccp v 3 v ol output-low voltage i out = 1500 a 0.1 v ccp v 3 i il input-leakage current 0 < v in < v ccp -10 10 a 1 , 3 c in input-pin capacitance 5 pf 2 , 3 c out i/o or output pin capacitance 5pf 2 , 3 c idsel idsel-pin capacitance 5 pf 2 , 3 l pin pin inductance 20 nh 2 , 3 notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tri-state outputs. 2. these values are typical va lues seen by the manufacturi ng process and are not tested. 3. for additional information, see the pci local bus specification , rev. 2.2. 4. please refer to the product specification update. table 27. usb v1.1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v 1 v il input-low voltage 0.8 v v oh output-high voltage i out = -6.1 * v oh ma 2.8 v v ol output-low voltage iout = 6.1 * v oh ma 0.3 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 2 notes: 1. please refer to the product specification update. 2. these values are typical values seen by the manufacturing process and are not tested
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 87 5.4.4 utopia-2 dc parameters 5.4.5 mii dc parameters table 28. utopia-2 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.5 v i oh output current at high voltage v oh > 2.4 v -8 ma i ol output current at low voltage v ol < 0.5 v 8 ma i il input-leakage current 0 < v in < v ccp -10 10 a 1 c in input-pin capacitance 5 pf 2 c out i/o or output pin capacitance 5pf 2 notes: 1. input leakage currents include hi-z output leakage for all bidirectional buffers with tri-state outputs. 2. these values are typical va lues seen by the manufacturi ng process and are not tested. table 29. mii dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4ma 0.4 v i oh output current at high voltage v oh > 2.4 v -8 ma i ol output current at low voltage v ol < 0.4 v 8 ma i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 note: 1. these values are typical va lues seen by the manufacturi ng process and are not tested.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 88 document number: 252479, revision: 005 5.4.6 mdio dc parameters 5.4.7 sdram bus dc parameters 5.4.8 expansion bus dc parameters table 30. mdio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 c inmdio input-pin capacitance 5 pf 1 note: 1. these values are typical values seen by the manufacturing process and are not tested. table 31. sdram bus dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v 1 v il input-low voltage 0.8 v 2 v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -5 5 a i ol output-leakage current 0 < v in < v ccp -5 5 a c inclk input-pin capacitance 4 pf 3 c io i/o-pin capacitance 5 pf 3 notes: 1. v ih overshoot: v ih (max) = v ccp + 2 v for a pulse width < 3 ns, and the pulse width cannot be greater than one third of the cycle rate. 2. v il undershoot: v il (min) = -2 v for a pulse width < 3 ns cannot be exceeded. 3. these values are typical values seen by the manufacturing process and are not tested. table 32. expansion bus dc parameters (sheet 1 of 2) symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v 1 notes: 1. test conditions were a 70 pf load to ground. 2. these values are typical values seen by the manufacturing process and are not tested.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 89 5.4.9 high-speed, serial inte rface 0 dc parameters 5.4.10 high-speed, serial interface 1 dc parameters v ol output-low voltage i out = 4ma 0.4 v 1 i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 2 table 33. high-speed, serial interface 0 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 note: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. table 34. high-speed, serial interface 1 dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -8 ma 2.4 v v ol output-low voltage i out = 8 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 note: 1. these values are typical va lues seen by the manufacturi ng process and are not tested. table 32. expansion bus dc parameters (sheet 2 of 2) symbol parameter conditions min. typ. max. units notes notes: 1. test conditions were a 70 pf load to ground. 2. these values are typical va lues seen by the manufacturi ng process and are not tested.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 90 document number: 252479, revision: 005 5.4.11 high-speed and console uart dc parameters 5.4.12 gpio dc parameters 5.4.13 jtag dc parameters table 35. uart dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 note: 1. these values are typical values seen by the manufacturing process and are not tested. table 36. gpio dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage for gpio 0 to gpio 13 i out = -16 ma 2.4 v v ol output-low voltage for gpio 0 to gpio 13 i out = 16 ma 0.4 v v oh output-high voltage for gpio 14 and gpio 15 i out = -4 ma 2.4 v v ol output-low voltage for gpio 14 and gpio 15 i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf table 37. jtag dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v v oh output-high voltage i out = -4 ma 2.4 v v ol output-low voltage i out = 4 ma 0.4 v i il input-leakage current 0 < v in < v ccp -10 10 a c in input-pin capacitance 5 pf 1 note: 1. these values are typical values seen by the manufacturing process and are not tested.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 91 5.4.14 reset dc parameters 5.5 ac specifications 5.5.1 clock signal timings 5.5.1.1 processor clock timings crystal oscillators require that good system-level design practices be followed for reliable start-up and oscillation. please refer to the intel ? ixp42x product line of network processors and ixc1100 control plane processor product line: crystal design considerations application note (document number 305588), and contact intel for the recommended intel ? ixp42x product line of network processors and ixc1100 control plane processor part number optimized for use with crystal oscillators. table 38. pwron_reset_n dc parameters symbol parameter conditions min. typ. max. units notes v ih input-high voltage 1.0 1.3 v the input voltage must not exceed 1.3v or long-term reliability may be adversely affected. v il input-low voltage 0.3 v i il input leakage current 0 < v in < 1.3v -500 10 a c in input capacitance 1 pf simulated results. table 39. device clock timings (oscillator reference) (sheet 1 of 2) symbol parameter min. nom. max. units notes v ih input-high voltage 2.0 v v il input-low voltage 0.8 v t frequency clock frequency for ixp42x product line and ixc1100 control plane processors crystal or oscillator. 33.33 mhz 1 , 4 u frequency clock tolerance over -40o c to 85o c. -50 50 ppm c in pin capacitance of ixp42x product line and ixc1100 control plane processors? inputs. 5pf c shunt c shunt is a crystal parameter sometimes referred to as the holder capacitance. 234pf notes: 1. this value could be an oscillator input or a se ries resonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pi n and leave the crystal output pin disconnected. 2. use the component values recommended by the crystal manufacturer. 3. this parameter applies when driving the clock input with an oscillator. 4. where the ixp42x product line or ixc1100 contro l plane processor is configured with an input reference-clock, the slew rate should never be fa ster than 2.5 v/ns to ensure proper pll operation. to help ensure proper pll operation at the slower slew rate, the vih and vil voltage levels need to be within the specified range at an input clock frequency of 33.33 mhz.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 92 document number: 252479, revision: 005 . c 1 load capacitance pf 2 c 2 load capacitance pf 2 t dc duty cycle 35 50 65 % 3 table 40. device clock timi ngs (crystal reference) symbol parameter min. nom. max. units notes v ih input-high voltage 1.9 v v il input-low voltage 1.6 v t frequency clock frequency for ixp42x product line and ixc1100 control plane processors crystal or oscillator. 33.33 mhz 1 , 4 u frequency clock tolerance over -40o c to 85o c. -50 50 ppm esr equivalent series resistance 60 ? c in pin capacitance of ixp42x product line and ixc1100 control plane processors? inputs. 5pf c shunt c shunt is a crystal parameter sometimes referred to as the holder capacitance. 23 4pf c 1 load capacitance pf 2 c 2 load capacitance pf 2 t dc duty cycle 35 50 65 % 3 notes: important note: please refer to the product specificati on update regarding new crystal specifications. 1. this value could be an oscillator input or a seri es resonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pi n and leave the crystal output pin disconnected. 2. use the component values recommended by the crystal manufacturer. 3. this parameter applies when driving the clock input with an oscillator. 4. where the ixp42x product line or ixc1100 contro l plane processor is configured with an input reference-clock, the slew rate should never be faster than 2.5 v/ns to ensure proper pll operation. to help ensure proper pll operation at the slower slew rate, the vih and vil voltage levels need to be within the specified range at an input clock frequency of 33.33 mhz. table 39. device clock timings (oscillator reference) (sheet 2 of 2) symbol parameter min. nom. max. units notes notes: 1. this value could be an oscillator input or a seri es resonant frequency from a crystal. if used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. use the component values recommended by the crystal manufacturer. 3. this parameter applies when driving the clock input with an oscillator. 4. where the ixp42x product line or ixc1100 contro l plane processor is configured with an input reference-clock, the slew rate should never be faster than 2.5 v/ns to ensure proper pll operation. to help ensure proper pll operation at the slower slew rate, the vih and vil voltage levels need to be within the specified range at an input clock frequency of 33.33 mhz.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 93 figure 14. typical connection to a crystal figure 15. typical connection to an oscillator xtal c 1 c 2 osc_in osc_out intel ? ixp42x product line / intel ? ixc1100 control plane processor b1677-03 oscillator osc_in osc_out intel ? ixp42x product line / intel ? ixc1100 control plane processor b1678-03
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 94 document number: 252479, revision: 005 5.5.1.2 pci clock timings 5.5.1.3 mii clock timings 5.5.1.4 utopia-2 clock timings 5.5.1.5 expansion bus clock timings table 41. pci clock timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t periodpciclk clock period for pci clock 30 15 ns t clkhigh pci clock high time 11 6 ns t clklow pci clock low time 11 6 ns t rise/fall rise and fall time requirements for pci clock 22ns table 42. mii clock timings symbol parameter min. nom. max. units notes t period100mbit clock period for tx and rx ethernet clocks 25 25 mhz t period10mbit clock period for tx and rx ethernet clocks 2.5 2.5 mhz t duty duty cycle for tx and rx ethernet clocks 35 50 65 % t rise/fall rise and fall time requirements for tx and rx ethernet clocks 2ns table 43. utopia-2 clock timings symbol parameter min. nom. max. units notes t period clock period for tx and rx utopia-2 clocks 33 mhz 1 t duty duty cycle for tx and rx utopia-2 clocks 40 50 60 % 1 t rise/fall rise and fall time requirements for tx and rx utopia-2 clocks 2ns 1 note: 1. the utopia interface can operate at a minimum frequency greater than 0 hz. table 44. expansion bus clock timings symbol parameter min. nom. max. units notes t period clock period for expansion-bus clock 66 mhz t duty duty cycle for expans ion-bus clock 40 50 60 % t rise/fall rise and fall time requirements for expansion-bus clock 2ns
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 95 5.5.2 bus signal timings the ac timing waveforms are shown in the following sections. 5.5.2.1 pci note: v hi = 0.6 v cc and v low = 0.2 v cc figure 16. pci output timing a9572-01 clk output delay t clk2out(b) v low v hi figure 17. pci input timing a9573-01 clk input inputs valid t hold t setup(b)
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 96 document number: 252479, revision: 005 5.5.2.2 usb interface for timing parameters, see the usb 1.1 specification. the ixp42x product line and ixc1100 control plane processors? usb 1.1 interface is a device or functio n controller only. the ixp42x product line and ixc1100 control plane processors? usb v 1.1 interface cannot be line-powered. table 45. pci bus signal timings symbol parameter 33 mhz 66 mhz units notes min. max. min. max. t clk2outb clock to output for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 2111 6ns 1 , 2 , 5 , 7 , 8 t clk2out clock to output for all point-to-point signals. this is the pci_gnt_n and pci_req_n(0) only. 2121 6ns 1 , 2 , 5 , 7 , 8 t setupb input setup time for all bused signals. this is the pci_ad[31:0], pci_cbe_n [3:0], pci_par, pci_frame_n, pci_irdy_n, pci_trdy_n, pci_stop_n, pci_devsel_n, pci_perr_n, pci_serr_n 73ns 4 , 6 , 7 , 8 t setup input setup time for all point-to- point signals. this is the pci_req_n and pci_gnt_n(0) only. 10, 12 5 ns 4 , 7 , 8 t hold input hold time from clock. 0 0 ns 4 , 7 , 8 t rst-off reset active-to-output float delay 40 40 ns 5 , 6 , 7 , 8 notes: 1. see the timing meas urement conditions. 2. parts compliant to the 3.3 v signaling environment. 3. req# and gnt# are point-to-point signals and hav e different output valid delay and input setup times than do bused signals. gnt# has a setup of 10 ns for 33 mhz and 5 ns for 66 mhz; req# has a setup of 12 ns for 33 mhz and 5 ns for 66 mhz. 4. rst# is asserted and de-asserted asyn chronously with respect to clk. 5. all pci outputs must be asynchronously driven to a tri-state value when rst# is active. 6. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 7. timing was tested with a 70-pf capacitor to ground. 8. for additional information, see the pci local bus specification , rev. 2.2.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 97 5.5.2.3 utopia-2 figure 18. utopia-2 input timings table 46. utopia-2 input timings values symbol parameter min. max. units notes t setup input setup prior to rising edge of clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 8ns t hold input hold time after the rising edge of the clock. inputs included in this timing are utp_ip_data[7:0], utp_ip_soc, and utp_ip_fci, and utp_op_fci. 1ns figure 19. utopia-2 output timings table 47. utopia-2 output timings values symbol parameter min. max. units notes t clk2out rising edge of clock to signal output. outputs included in this timing are utp_ip_data[3:0], utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], and utp_op_addr[3:0]. 17 ns 1 t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are utp_ip_data[3:0], utp_op_soc, utp_op_fco, utp_ip_fco, utp_op_data[7:0], and utp_op_addr[3:0]. 1ns 1 note: 1. timing was tested with a 70-pf capacitor to ground. a9578-01 thold tsetup clock signals a9579-01 tclk2out tholdout clock signals
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 98 document number: 252479, revision: 005 5.5.2.4 mii figure 20. mii output timings table 48. mii output timings values symbol parameter min. max. units notes t 1 clock to output delay for eth_txdata and eth_txen. 017ns 1 t 2 eth_txdata and eth_txen hold time after eth_txclk. 2 ns note: 1. these values satisfy the mii specification requ irement of 0 ns to 25 ns clock to output delay. figure 21. mii input timings table 49. mii input timings values symbol parameter min. max. units notes t 3 eth_rxdata and eth_rxdv setup time prior to rising edge of eth_rxclk 5.5 ns 1 , 2 t 4 eth_rxdata and eth_rxdv hold time after the rising edge of eth_rxclk 0 ns 1 , 2 , 3 notes: 1. these values satisfy the mii specificati on requirement of 10-ns setup and hold time. 2. timing tests were performed with a 70-pf capacitor to ground. 3. this parameter has been simulated but has not been fully tested. a9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs t 1 t 2 a9581-01 eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs t 4 t 3
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 99 5.5.2.5 mdio figure 22. mdio output timings note: npe is sourcing mdio. figure 23. mdio input timings note: phy is sourcing mdio. table 50. mdio timings values symbol parameter min. max. units notes t1 eth_mdio, clock to output timing with respect to rising edge of eth_mdc clock eth_mdc/2 + 10 ns ns t2 eth_mdio output hold timing after the rising edge of eth_mdc clock 10 ns t3 eth_mdio input setup prior to rising edge of eth_mdc clock 2 ns t4 eth_mdio hold time after the rising edge of eth_mdc clock 0 ns 1 t5 eth_mdc clock period 125 500 ns note: 1. this parameter is guaranteed by design but has not been 100% tested. a9582-02 eth_mdc eth_mdio t 1 t 2 a9583-02 eth_mdc eth_mdio t 3 t 5 t 4
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 100 document number: 252479, revision: 005 5.5.2.6 sdram bus figure 24. sdram input timings table 51. sdram input timings values symbol parameter min. max. units notes t setup input setup prior to rising edge of clock. inputs included in this timing are sdm_dq[31:0] (during a read operation). 1.4 ns t hold input hold time after the rising edge of the clock. inputs included in this timing are sdm_dq[31:0] (during a read operation). 1.5 ns figure 25. sdram output timings table 52. sdram output timings values symbol parameter min. max. units notes t clk2out rising edge of clock-to-signal output. outputs included in this timing are sdm_addr[12:0], sdm_ba[1:0], sdm_dqm[3:0], sdm_cke, sdm_we_n, sdm_cs_n[1:0], sdm_cas_n, sdm_ras_n, sdm_dq[31:0] (during a write operation). 5.5 ns 1 t holdout signal output hold time after the rising edge of the clock. outputs included in this timing are sdm_dq[31:0] (during a write operation). 1.5 ns 1 note: 1. timing test were performed with a 70-pf load to ground.
a9584-01 t clk2out t holdout data valid clock signals
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 101 5.5.2.7 expansion bus figure 26. signal timing with respect to clock rising edge table 53. signal timing with respect to clock rising edge symbol description min. max. units notes t ov control signal and data output valid after clock rising edge 15 ns t setup input setup time with respect to clock rising edge. 3 ns 1 t hold input hold time with respect to clock rising edge. 2 ns 1 note: 1. the setup and hold timing values are for all modes. b4870-002 ex_clk ex_cs_n[0] ex_addr[23:0] ex_rd_n ex_data[15:0] valid address t setup t hold 1-4 cycles 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n ex_wr_n ex_data[15:0] data out data in t ov t ov t ov
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 102 document number: 252479, revision: 005 figure 27. intel ? multiplexed read mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_data[15:0] 2-5 cycles ale extended 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles intel ? multiplexed read mode valid data ex_ale valid address t recov t rdhold ex_rd_n t rdsetup t alepulse t ale2valcs t1 t2 t3 t4 t5 ex_iowait_n valid address b3747-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 103 figure 28. intel ? multiplexed write mode ex_clk ex_cs_n[0] ex_addr[23:0] 2-5 cycles ale extended 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles ex_ale ex_wr_n valid address t recov ex_data[15:0] valid data t dval2valwrt t ale2addrhold t wrpulse t alepulse t ale2valcs t1 t2 t3 t4 t5 ex_iowait_n t dhold2afterwr valid address b3748-001 intel ? multiplexed write mode
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 104 document number: 252479, revision: 005 table 54. intel ? multiplexed mode values symbol parameter min. max. units notes talepulse pulse width of ex_ale (addr is valid at the rising edge of ex_ale) 141cycles 1 , 7 tale2addrhold valid address hold time after from falling edge of ex_ale 1 1 cycles 1 , 2 , 7 tdval2valwrt write data valid prior to ex_wr_n falling edge 1 4 cycles 3 , 7 twrpulse pulse width of the ex_wr_n 1 16 cycles 4 , 7 tdholdafterwr valid data after the rising edge of ex_wr_n 1 4 cycles 5 , 7 tale2valcs valid chip select after the falling edge of ex_ale 1 4 cycles 7 trdsetup data valid required before the rising edge of ex_rd_n 15 ns trdhold data hold required after the rising edge of ex_rd_n 0 ns trecov time needed between successive accesses on expansion interface. 116cycles 6 notes: 1. the ex_ale signal is extended from 1 to 4 c ycles based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at 1 cycle. 2. setting the address phase parameter (t1) will adjust the duration that t he address appears to the ex ternal device. 3. setting the data setup phase parameter (t2) will adjus t the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data w ill be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adju st the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 105 figure 29. intel ? simplex read mode figure 30. intel ? simplex write mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_rd_n ex_data[15:0] intel ? simplex read mode valid data valid address t recov t rdsetup t rdhold 1-4 cycles 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n b3749-002 ex_clk ex_cs_n[0] ex_addr[23:0] intel ? simplex write mode ex_wr_n valid address t recov ex_data[15:0] valid data t dval2valwrt t addr2valcs t wrpulse 1-4 cycles 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n t dhold2afterwr b3750-002
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 106 document number: 252479, revision: 005 table 55. intel simplex mode values symbol parameter min. max. units notes t addr2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valwrt write data valid prior to ex_wr_n falling edge 1 4 cycles 3 , 7 t wrpulse pulse width of the ex_wr_n 1 16 cycles 4 , 7 t dholdafterwr valid data after the rising edge of ex_wr_n 1 4 cycles 5 , 7 t rdsetup data valid required before the rising edge of ex_rd_n 15 ns t rdhold data hold required after the rising edge of ex_rd_n 0 ns t recov time required between successive accesses on the expansion interface. 1 16 cycles 6 notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adj ust the duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will ad just the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) wi ll adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 107 figure 31. motorola* multiplexed read mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_data[15:0] ex_ale valid address t recov t rdhold ex_rd_n (exp_mot_rnw) ex_wr_n (exp_mot_ds_n) t rdsetup t alepulse t ale2valcs 2-5 cycles ale extended 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n b3751-001 motorola* multiplexed read mode valid data valid address
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 108 document number: 252479, revision: 005 figure 32. motorola* multiplexed write mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_rd_n (exp_mot_rnw) ex_ale ex_wr_n (exp_mot_ds_n) valid address t recov ex_data[15:0] t dval2valds t ale2addrhold t dspulse t alepulse t ale2valcs 2-5 cycles ale extended 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n b3752-001 motorola* mu ltiplexed write mode valid data valid address
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 109 table 56. motorola* multiplexed mode values symbol parameter min. max. units notes t alepulse pulse width of ex_ale (addr is valid at the rising edge of ex_ale) 14cycles 1 , 7 t ale2addrhold valid address hold time after from falling edge of ex_ale 1 1 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 t ale2valcs valid chip select after the falling edge of ex_ale 1 4 cycles 7 t rdsetup data valid required before the rising edge of exp_mot_ds_n 15 ns t rdhold data hold required after the rising edge of exp_mot_ds_n 0 ns t recov time needed between successive accesses on expansion interface. 116cycles 6 notes: 1. the ex_ale signal is extended from 1 to 4 c ycles based on the programming of the t1 timing parameter. the parameter tale2addrhold is fixed at 1 cycle. 2. setting the address phase pa rameter (t1) will adjust th e duration t hat the addr ess appears to the external device. 3. setting the data setup phase parameter (t2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data w ill be available during this time as well. 5. setting the data hold strobe phase parameter (t4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parameter (t5) will adj ust the duration between su ccessive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 110 document number: 252479, revision: 005 figure 33. motorola* simplex read mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_iowait_n ex_data[15:0] valid data ex_ale valid address t recov t rdhold ex_rd_n (exp_mot_rnw) ex_wr_n (exp_mot_ds_n) t rdsetup t ad2valcs 1-4 cycles 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 b3753-001 motorola* simplex read mode
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 111 figure 34. motorola* simplex write mode ex_clk ex_cs_n[0] ex_addr[23:0] ex_rd_n (exp_mot_rnw) ex_ale ex_wr_n (exp_mot_ds_n) valid address t recov ex_data[15:0] valid data t dval2valds t dspulse t ad2valcs t dhold2afterds 1-4 cycles 1-4 cycles 1-16 cycles 1-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_iowait_n b3754-001 motorola* simplex write mode
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 112 document number: 252479, revision: 005 table 57. motorola* simplex mode values symbol parameter min. max. units notes t ad2valcs valid address to valid chip select 1 4 cycles 1 , 2 , 7 t dval2valds write data valid prior to exp_mot_ds_n falling edge 1 4 cycles 3 , 7 t dspulse pulse width of the exp_mot_ds_n 1 16 cycles 4 , 7 t dholdafterds valid data after the rising edge of exp_mot_ds_n 1 4 cycles 5 , 7 t rdsetup data valid required before the rising edge of exp_mot_ds_n 15 ns t rdhold data hold required afte r the rising edge of exp_mot_ds_n 0ns t recov time required between successive accesses on the expansion interface. 116cycles 6 notes: 1. ex_ale is not valid in simplex mode of operation. 2. setting the address phase parameter (t1) will adjust th e duration that the address appears to the external device. 3. setting the data setup phase parameter (t2) will ad just the duration that the data appears prior to a data strobe (read or write) to an external device. 4. setting the data strobe phase parameter (t3) will adjust the duration that the data strobe appears (read or write) to an external device. data will be available during this time as well. 5. setting the data hold strobe phase parameter (t4) wi ll adjust the duration that the chip selects, address, and data (during a write) will be held. 6. setting the recovery phase parame ter (t5) will adjust the durati on between successive accesses on the expansion interface. 7. one cycle is the period of the expansion bus clock. 8. clock to output delay for all si gnals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 113 figure 35. hpi-8 mode read accesses ex_clk ex_cs_n[0] (hcs_n) ex_addr[23:0] (hcntl) ex_rdy_n (hrdy) ex_data[15:0] (hdout) ex_rd_n (hr_w_n) valid address t recov t data_setup t cs2hds1val t addsetup t1 t2 t3 t4 t5 ex_addr[0] (hbil) ex_wr_n (hds1_n) t hds1_pulse t data_hold valid data 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles b3742-001 hpi-8 mode read accesses
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 114 document number: 252479, revision: 005 figure 36. hpi-8 mode write accesses ex_clk ex_cs_n[0] (hcs_n) ex_addr[23:0] (hcntl) ex_rdy_n (hrdy) ex_data[15:0] (hdin) valid data ex_rd_n (hr_w_n) valid address t recov t data_setup t cs2hds1val t addsetup t1 t2 t3 t4 t5 ex_addr[0] (hbil) ex_wr_n (hds1_n) t hds1_pulse t data_hold 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles hpi-8 mode write accesses b3746-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 115 table 58. hpi timing symbol description state description min. max. unit notes t1 address timing 3 4 cycles 1 , 5 , 6 t2 setup/chip select timing 3 4 cycles 2 , 6 t3 strobe timing 2 16 cycles 3 , 5 , 6 t4 hold timing 3 4 cycles 6 t5 recovery phase 2 17 cycles 6 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. th is setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de- active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground. table 59. hpi-8 mode write access values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1 , 5 , 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5 , 6 t hds1_pulse pulse width of the hds1 data strobe 4 5 cycles 2 , 4 , 5 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. th is setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de- active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in t he access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 116 document number: 252479, revision: 005 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3 , 5 , 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3 , 6 t recov time required between successive accesses on the expansion interface. 2 17 cycles 4 , 6 table 59. hpi-8 mode write access values symbol parameter min. max. units notes notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de- active. 4. setting the recovery phase parame ter (t5) will adjust the durati on between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 117 table 60. hpi-16 multiple xed write accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1 , 5 , 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5 , 6 t hds1_pulse pulse width of the hds1 data strobe. 4 5 cycles 2 , 4 , 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3 , 5 , 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3 , 6 t recov time required between successive accesses on the expansion interface. 217cycles 4 , 6 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. th is setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase fo r at least one clock pul se after the hrdy is de- active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in the access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 118 document number: 252479, revision: 005 figure 37. hpi-16 multiplexed write mode ex_clk ex_cs_n[0] (hcs_n) ex_addr[23:0] (hcntl) ex_rdy_n (hrdy) ex_data[15:0] (hdin) valid data ex_rd_n (hr_w_n) valid address t recov t data_setup t addsetup 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles t1 t2 t3 t4 t5 ex_wr_n (hds1_n) t hds1_pulse t data_hold t cs2hds1val hpi-16 multiplex write mode b3743-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 119 table 61. hpi-16 multiplexed read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asserted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1 , 5 , 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5 , 6 t hds1_pulse pulse width of the hds1 data strobe. 4 5 cycles 2 , 4 , 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 45 cycles 3 , 5 , 6 t recov time required between successive accesses on the expansion interface. 217cycles 4 , 6 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. th is setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase fo r at least one clock pulse after the hrdy is de-active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in t he access. the interface wi ll not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 120 document number: 252479, revision: 005 figure 38. hpi-16 multiplex read mode ex_clk ex_cs_n[0] (hcs_n) ex_addr[23.0] (hcntl) ex_rdy_n (hrdy) ex_data[15:0] (hdout) valid data ex_rd_n (hr_w_n) valid address t recov t data_setup t cs2hds1val t addsetup t1 t2 t3 t4 t5 ex_wr_n (hds1_n) t hds1_pulse 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles hpi-16 multiplex read mode b3741-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 121 table 62. hpi-16 simplex read accesses values symbol parameter min. max. units notes t add_setup valid time that address is asse rted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1 , 5 , 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5 , 6 t hds1_pulse pulse width of the hds1 data strobe. 4 5 cycles 2 , 4 , 5 t data_setup data is valid from the time from of the falling edge of hds1_n to when the data is read. 45 cycles 3 , 5 , 6 t recov time required between successive accesses on the expansion interface. 217cycles 4 , 6 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. th is setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase for at least one clock pulse after the hrdy is de- active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in t he access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 122 document number: 252479, revision: 005 figure 39. hpi-16 simplex read mode ex_clk ex_cs_n[0] (hcs_n) ex_addr[23:0] (hcntl) ex_rdy_n (hrdy) ex_data[15:0] (hdout) valid data ex_rd_n (hr_w_n) valid address t recov t data_setup t cs2hds1val t addsetup t1 t2 t3 t4 t5 ex_wr_n (hds1_n) t hds1_pulse 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles hpi-16 simplex read mode b3744-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 123 table 63. hpi-16 simplex write accesses values symbol parameter min. max. units notes t add_setup valid time that address is asse rted on the line. the address is asserted at the same time as chip select. 11 45 cycles 1 , 5 , 6 t cs2hds1val delay from chip select being active and the hds1 data strobe being active. 3 4 cycles 5 , 6 t hds1_pulse pulse width of the hds1 data strobe. 4 5 cycles 2 , 4 , 5 t data_setup data valid prior to the rising edge of the hds1 data strobe. 4 5 cycles 3 , 5 , 6 t data_hold data valid after the rising edge of the hds1 data strobe. 4 36 cycles 3 , 6 t recov time required between successive accesses on the expansion interface. 217cycles 4 , 6 notes: 1. the address phase parameter (t1) must be set to a minimum value of 2. this value allows three t clocks for the address phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the address phase for at least one clock pulse after the hrdy is de- active. 2. the data setup phase parameter (t2) must be set to a minimum value of 2. this value allows three t clocks for setup phase. 3. the data strobe phase parameter (t3) must be set to a minimum value of 1. this value allows two t clocks for the data phase. this setting is required to ensure that in the event of an hrdy, the intel ? ixp42x product line and intel ? ixc1100 control plane processors has had sufficient time to recognize the hrdy and hold the data setup phase fo r at least one clock pulse after the hrdy is de- active. 4. setting the recovery phase parameter (t5) will adjust the duration between successive accesses on the expansion bus interface. 5. hrdy can be asserted by the dsp at any point in t he access. the interface will not leave states t1 or t3 until hrdy is de-active. 6. one cycle is the period of the expansion bus clock. 7. timing tests were performed with a 70-pf capacitor to ground.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 124 document number: 252479, revision: 005 figure 40. hpi-16 simplex write mode ex_clk ex_cs_n[0] (hcs_n) ex_addr[23:0] (ha) ex_rdy_n (hrdy) ex_data[15:0] (hdin) valid data ex_rd_n (hr_w_n) valid address t recov t data_setup t add_setup t1 t2 t3 t4 t5 ex_wr_n (hds1_n) t hds1_pulse t cs2hds1val 3-4 cycles 3-4 cycles 2-16 cycles 2-4 cycles 1-16 cycles hpi-16 simplex write mode b3745-001
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 125 5.5.2.7.1 ex_iowait_n the ex_iowait_n signal is availabl e to be shared by devices att ached to chip selects 0 through 7 and is used as required by slow devices. if the external device asserts ex _iowait_n during the strobe phase of a read transfer, the controller will hold in that phas e until the ex_iowait_n goes false. at that time, the controller will immediately transition to the hold phase regardless of the setting of the programming parameter (t3) for the strobe phase. the ex_iowait_n signal only affects the interface du ring the strobe phase of a read transfer. if chip selects 4 through 7 are conf igured in hpi mode of operati on, each chip select will have a corresponding hrdy signal called ex_rdy. the pola rity of the ready signal is programmable. chip select 4 corresponds to ex_rdy signal 0 and chip select 7 corresponds to ex_rdy signal 3. 5.5.2.8 high-speed, serial interfaces figure 41. high-speed, serial timings a9594-01 hss_txclk/ hss_rxclk 1 hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ rxdata (positive edge) as inputs: valid data hss_ rxdata (negative edge) hss_(tx or rx)frame (positive edge) hss_(tx or rx)frame (negative edge) hss_ txdata (positive edge) hss_ txdata (negative edge) as outputs: valid data t1 t3 t4 valid data valid data t6 t5 t7 t8 t2 t9
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 126 document number: 252479, revision: 005 for more information on the hss jitter specifications see the intel ? ixp42x product line of network processors and ixc1100 contro l plane processor developer?s manual. table 64. high-speed, serial timing values symbol parameter min. max. units notes t1 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the rising edge of clock 5ns 1 , 2 , 3 t2 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the rising edge of clock 0ns 1 , 2 , 3 t3 setup time of hss_txframe, hss_rxframe, and hss_rxdata prior to the falling edge of clock 5ns 1 , 2 , 3 t4 hold time of hss_txframe, hss_rxframe, and hss_rxdata after the falling edge of clock 0ns 1 , 2 , 3 t5 rising edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 4 t6 falling edge of clock to output delay for hss_txframe, hss_rxframe, and hss_txdata 15 ns 1 , 3 , 4 t7 output hold delay after rising edge of final clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t8 output hold delay after fa lling edge of fi nal clock for hss_txframe, hss_rxframe, and hss_txdata 0ns 1 , 3 , 4 t9 hss_txclk period and hss_rxclk period 1/8.192 mhz 1/512 khz ns 5 notes: 1. hss_txclk and hss_rxclk may be coming from ex ternal independent sources or being driven by the ixp42x product line and ixc1100 control pl ane processors. the signals are shown to be synchronous for illustrative purposes and are not required to be synchronous. 2. applicable when the hss_rxframe and hss_tx frame signals are being dr iven by an external source as inputs into the ixp42x product li ne and ixc1100 control plane processors. always applicable to hss_rxdata. 3. the hss_rxframe and hss_txframe can be configured to accept data on the rising or falling edge of the given reference clock. hss_rxfr ame and hss_rxdata signals are synchronous to hss_rxclk and hss_txframe and hss_txdata signals are synchronous to the hss_txclk. 4. applicable when the hss_rxframe and hss_tx frame signals are being dr iven by the ixp42x product line and ixc1100 control plane processors to an external source. always applicable to hss_txdata. 5. the hss_txclk can be configured to be driven by an external source or be driven by the ixp42x product line and ixc1100 control plane processors. the slowest clock speed that can be accepted or driven is 512 khz. the maximum clock speed that can be accepted or driven is 8.192 mhz. the clock duty cycle accepted will be 50/50 + 20%. 6. timing tests were performed with a 70-pf capacitor to ground and a 10-k ? pull-up resistor.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 127 5.5.2.9 jtag figure 42. boundary-scan general timings figure 43. boundary-scan reset timings table 65. boundary-scan interface timings values symbol parameter conditions min. typ. max. units notes t bscl jtag_tck low time 50 ns 2 t bsch jtag_tck high time 50 ns 2 t bsis jtag_tdi, jtag_tms setup time to rising edge of jtag_tck 10 ns t bsih jtag_tdi, jtag_tms hold time from rising edge of jtag_tck 10 ns t bsoh jtag_tdo hold time after falling edge of jtag_tck 1.5 ns 1 t bsod jtag_tdo clock to output from falling edge of jtag_tck 40 ns 1 t bsr jtag_trst_n reset period 30 ns t bsrs jtag_tms setup time to rising edge of jtag_trst_n 10 ns t bsrh jtag_tms hold time from rising edge of jtag_trst_n 10 ns notes: 1. tests completed with a tbd pf load to ground on jtag_tdo. 2. jtag_tck may be stopped indefinitely in either the low or high phase. b0416-01 t bsel t bsis t bsih t bsch jtg_tck jtg_tms, jtg_tdi jtg_tdo t bsoh t bsod a9597-01 t bsr t bsrs t bsrh jtg_trst_n jtg_tms
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 128 document number: 252479, revision: 005 5.5.3 reset timings figure 44. reset timings v ccp v cc pll_lock pwron_reset_n reset_in_n ex_addr[23:0] ex_addr[23:0]-pull up/down cfg settings to be captured cfg settings to be captured ixp42x/ixc1100 drives outputs t release_pwron_rst_n t ex_addr_setup t release_rst_n t pll_lock t ex_addr_hold b1679-03
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 129 5.6 power sequence the 3.3-v i/o voltage (v ccp ) must be powered up 1 s before the core voltage (v cc ). the ixp42x product line and ixc1100 control plane processors? core voltage (v cc ) must never become stable prior to the 3.3-v i/o voltage (v ccp ). the v ccosc , v ccpll1 , and v ccpll2 voltages follow the v cc power-up pattern. the v ccoscp follows the v ccp power-up pattern. the value for t power_up must be at least 1 s. the t power_up timing parameter is measured from v ccp at 3.3 v and v cc at 1.3 v. there are no power-down re quirements for the ixp42x product line and ixc1100 control plane processors. table 66. reset timings table parameters symbol parameter min. typ. max. units note t release_pwron_rst_n minimum time required to hold the pwron_rst_n at logic 0 state after stable power has been applied to the ixp42x product line and ixc1100 control plane processors. when using a crystal to drive the processors? system clock. (osc_in and osc_out) 500 ms 1 t release_reset_in_n minimum time required to hold the reset_in_n at logic 0 state after pwron_rst_n has been released to a logic 1 state. the reset_in_n signal must be held low when the pwron_rst_n signal is held low. 10 ns t pll_lock maximum time for pll_lock signal to drive to logic 1 after reset_in_n is driven to logic 1 state. the boot sequence does not occur until this period is complete. 10 s t ex_addr_setup minimum time for the ex_addr signals to drive the inputs prior to reset_in_n being driven to logic 1 state. this is used for sampling configuration information. 50 ns 2 t ex_addr_hold minimum/maximum time for the ex_addr signals to drive the inputs prior to pll_lock being driven to logic 1 state. this is used for sampling configuration information. 020ns 2 t warm_reset minimum time required to drive reset_in_n signal to logic 0 in order to cause a reset after the ixp42x product line and ixc1100 control plane processors has been in normal operation. the power must remain stable and the pwron_rst_n signal must remain stable. 500 ns notes: 1. t release_pwron_rst_n is the time required for the internal oscillator to reach stability. when an external oscillator is being used in place of a crystal, the 500-ms delay is not required. 2. the expansion bus address is c aptured as a derivative of the reset_in_n signal going high. when a programmable-logic device is used to drive the ex_addr signals instead of pull-downs, the signals must be active until pll_lock is active. 3. pll_lock is deasserted immediately when watc hdog timer event occurs, or when reset_in_n is asserted, or when pwron_rst_n is asserted. pll_ lock remains deasserted for ~24 ref_clocks after the watchdog reset is deasserted (internal to t he chip). a ref clock time period is 1/clkin.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 130 document number: 252479, revision: 005 figure 45. power-up sequence timing b2263-01 1 2 3 4 v o l t s time v ccp v cc t power_up
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 131 5.7 i cc and total average power table 67. i cc and total average power ? commercial temperature range speed symbol description typical current and power 1 max current 2 average max power 2 266 mhz i cc core supply current 0.70a 0.725a 1.0w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.5w 1.9w 400 mhz i cc core supply current 0.75a 0.800a 1.09w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.57w 2.0w 533 mhz i cc core supply current 0.82a 1.00a 1.4w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.66w 2.3w notes: 1. typical current icc and iccp are not tested. typical currents were measured on the intel ? ixdp425 / ixcdp1100 development platform at room temperature usi ng typical sku silicon samples. a smartbits* tester was used in a router application running linux* on the kixdp425bd. two ethernet npes, and two ethernet controller pci cards were used in this router application. typical case power su pply voltages vcc =1.327v, vccp = 3.363 v. typical operating temperature is room temperature. 2. maximum voltages: vcc = 1.365 v, vccp = 3.465 v, vccosc= 1.365 v, vccpll1= 1.365 v, vccpll2= 1.365 v, maximum capacitive loading on all i/o pins of 50 pf. maximum icc and iccp are steady state currents at maximum operating temperature.
intel ? ixp42x product line of network processors and ixc1100 control plane processor march 2005 datasheet 132 document number: 252479, revision: 005 table 68. i cc and total average power ? extended temperature range speed symbol description typical current and power 1 max. current 2 average max. power 2 266 mhz i cc core supply current 0.70a 0.95a 1.3w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.5w 2.2w 400 mhz i cc core supply current 0.75a 1.05a 1.43w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.57w 2.33w 533 mhz i cc core supply current 0.82a 1.15a 1.57w i ccp i/o supply current 0.17a 0.26a 0.9w p total total average power both supplies 1.66w 2.47w notes: 1. typical current icc and iccp are not tested. typical currents were measured on the intel ? ixdp425 / ixcdp1100 development platform at room tem perature using typical sku silicon samples. a smartbits* tester was used in a router applicat ion running linux on the kixdp425bd. two ethernet npes, and two ethernet controller pci cards were us ed in this router applicat ion. typical case power supply voltages vcc = 1.327 v, vccp = 3.363 v. typical operating temperature is room temperature. 2. maximum voltages: vcc = 1.365 v, vccp = 3.465 v, vccosc= 1.365 v, vccpll1= 1.365 v, vccpll2= 1.365 v, maximum capacitive loading on al l i/o pins of 50 pf. maximum icc and iccp are steady state currents at maximum operating temperature.
intel ? ixp42x product line of network processors and ixc1100 control plane processor datasheet march 2005 document number: 252479, revision: 005 133 6.0 ordering information for ordering information, please contact your local intel sales representative.
intel ? ixp42x product line of network processors and ixc1100 control plane processor this page is intentionally left blank. march 2005 datasheet 134 document number: 252479, revision: 005

▲Up To Search▲

Price & Availability of FWIXP420BC

	To Download FWIXP420BC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .